6.1.12 TDM clock or SDHC/USB selection register
(CPLD_TDMCLK_MUX_SEL)
Use this register to select TDM clock or SDHC/USB.
Address: 0h base + Bh offset = Bh
Bit
0
1
2
3
4
5
6
7
Read
Write
Reset
0
0
0
0
0
0
0
0
CPLD_TDMCLK_MUX_SEL field descriptions
Field
Description
0
TDMCLK_
SDHC_USB_SEL
TDM clock or SDHC/USB selection
0
TDM_CLK
1
SDHC/USB
1–7
-
This field is reserved.
6.1.13 SDHC or SPI_CS selection register
(CPLD_SDHC_SPICS_SEL)
Use this register to select SDHC or SPI_CS.
Address: 0h base + Ch offset = Ch
Bit
0
1
2
3
4
5
6
7
Read
Write
Reset
0
0
0
0
0
0
0
0
CPLD_SDHC_SPICS_SEL field descriptions
Field
Description
0
SDHC_SPICS_
SEL
SDHC or SPI_CS selection
0
SDHC
1
SPI_CS
1–7
-
This field is reserved.
Chapter 6 CPLD Programming
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 0, 08/2015
Freescale Semiconductor, Inc.
59
