6.1.9 System clock single-ended or differential input selection
register (CPLD_SYSCLK_SEL)
Use this register to specify whether the system clock has single-ended input or
differential input.
Address: 0h base + 8h offset = 8h
Bit
0
1
2
3
Read
Write
Reset
0
0
0
0
Bit
4
5
6
7
Read
Write
Reset
0
0
0
0
CPLD_SYSCLK_SEL field descriptions
Field
Description
0
SYSCLK_IN_
SEL
System clock input selection
0
System clock differential input
1
System clock single-ended input
1–7
-
This field is reserved.
6.1.10 UART1 output selection register (CPLD_UART_SEL)
Use this register to specify output for UART1.
Address: 0h base + 9h offset = 9h
Bit
0
1
2
3
4
5
6
7
Read
Write
Reset
0
0
0
0
0
0
0
0
CPLD_UART_SEL field descriptions
Field
Description
0
UART1_OUT_
SEL
UART1 output selection
Table continues on the next page...
Chapter 6 CPLD Programming
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 0, 08/2015
Freescale Semiconductor, Inc.
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