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Chapter 5

Debug and Input/Output

This chapter contains the following sections:

•

ARM/JTAG architecture

•

•

5.1 ARM/JTAG architecture

The ARM/JTAG architecture is shown in the figure below.

QorIQ LS1043A Reference Design Board Reference Manual, Rev. 0, 08/2015

Freescale Semiconductor, Inc.

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Summary of Contents for QorIQ LS1043A

Page 1: ...ing on the information therein All referenced brands product names service names and trademarks are the property of their respective owners 00000005981LF 000 EOS Power Buy Now We have 45 000 LP502030...

Page 2: ...QorIQ LS1043A Reference Design Board Reference Manual Document Number LS1043ARDBRM Rev 0 08 2015...

Page 3: ...QorIQ LS1043A Reference Design Board Reference Manual Rev 0 08 2015 2 Freescale Semiconductor Inc...

Page 4: ...NAND flash memory 20 2 3 Serial interfaces 20 2 3 1 UART interface 21 2 3 2 eSDHC interface 21 2 3 3 DSPI interface 23 2 4 Ethernet interface 24 2 4 1 MII buses 25 2 5 SerDes interface 26 2 5 1 Mini...

Page 5: ...mperature anode and cathode 45 Chapter 5 Debug and Input Output 5 1 ARM JTAG architecture 47 5 2 CMSIS DAP 48 5 3 GPIOs 49 Chapter 6 CPLD Programming 6 1 CPLD memory map register definitions 51 6 1 1...

Page 6: ...nce clock input selection register CPLD_SD1REFCLK_SEL 58 6 1 12 TDM clock or SDHC USB selection register CPLD_TDMCLK_MUX_SEL 59 6 1 13 SDHC or SPI_CS selection register CPLD_SDHC_SPICS_SEL 59 6 1 14 S...

Page 7: ...QorIQ LS1043A Reference Design Board Reference Manual Rev 0 08 2015 6 Freescale Semiconductor Inc...

Page 8: ...number LS1043ARDB PA to order the LS1043ARDB You can perform the following operations using the LS1043ARDB onboard resources and debugging devices Upload and run code Set breakpoints Display memory a...

Page 9: ...ly voltage for UART I2C DMA EC Ethernet controllers ECC Error checking and correction EEPROM Electrically erasable programmable ROM EMI Electromagnetic interference eMMC Embedded multimedia card eSDHC...

Page 10: ...nt interface RCW Reset configuration word REFCLK Reference clock clock synthesizer input value RGMII Reduced gigabit media independent interface ROM Read only memory RTC Real time clock RTS Request to...

Page 11: ...al documents available for more information on the LS1043ARDB Table 1 2 Related documentation Document Description LS1043ARDB Quick Start LS1043ARDBQS Describes the LS1043ARDB hardware kit and lists t...

Page 12: ...ash 16 bit data bus 1 8 V One 512 MB SLC NAND flash with ECC support 1 8 V CPLD connection 8 bit registers in CPLD to configure some mux demux selections eSDHC SDHC port connects directly to a full SD...

Page 13: ...DB are given below 1 0 V for core VDD and USB SVDD 1 2 V for GVDD 1 8 V for LS1043A PROG_SFP and PROG_MTR POVDD 1 8 V and 3 3 V for CPLD 1 35 V for XVDD 1 0 V for SVDD 1 8 V for LS1043A general I O 3...

Page 14: ...1 LS1043A processor block diagram The figure below shows the LS1043ARDB block diagram Chapter 1 Introduction QorIQ LS1043A Reference Design Board Reference Manual Rev 0 08 2015 Freescale Semiconducto...

Page 15: ...2 LS1043ARDB block diagram 1 5 Board drawings The figure below shows the LS1043ARDB top view Board drawings QorIQ LS1043A Reference Design Board Reference Manual Rev 0 08 2015 14 Freescale Semiconduc...

Page 16: ...igure 1 3 LS1043ARDB top view The figure below shows the LS1043ARDB bottom view Chapter 1 Introduction QorIQ LS1043A Reference Design Board Reference Manual Rev 0 08 2015 Freescale Semiconductor Inc 1...

Page 17: ...Figure 1 4 LS1043ARDB bottom view Board drawings QorIQ LS1043A Reference Design Board Reference Manual Rev 0 08 2015 16 Freescale Semiconductor Inc...

Page 18: ...ture DDR interface IFC interface Serial interfaces Ethernet interface SerDes interface USB interface I2C interface 2 1 DDR interface The LS1043ARDB supports high speed DRAM with 2 GB double data rate...

Page 19: ...B integrated flash controller IFC has the following features Supports 1 8 V I O voltage Implements little endian support Supports 28 bit addressing and 16 bit data bus Supports GPCM NOR and NAND FCM S...

Page 20: ...DIP switches to allow dynamic reconfiguration of the IFC boot device which addresses IFC_CS_B 0 only The table below summarizes the IFC chip select routing Table 2 1 IFC chip select device mapping SW...

Page 21: ...2 NAND flash memory The LS1043ARDB has an ONFI 1 0 compatible Micron NAND flash memory MT29F4G08ABBDAH4 ITX with 512 MB size and 8 bit data bus The NAND flash memory is powered from a 1 8 V power sup...

Page 22: ...channels to both terminal and host computers The transceivers are connected to the dedicated UART ports on the LS1043ARDB by 4 wires They support RTS CTS flow control The table below describes the LS1...

Page 23: ...3 8 0 1 SPI_CS0_B K22 MCU TDM riser card SPI_CS1_B SPI_CS2_B SPI_CS3_B EVDD 1 8 V SW3 5 EVDD EVDD 3 3 V 1 0 SD card Pin 1 Pin 2 Pin 6 Pin 4 Pin 8 Pin 5 Pin 9 Pin 7 Pin 3 LS1043A SPI_MOSI SPI_MISO SPI_...

Page 24: ...S1043A SPI_CS 0 3 are muxed with LS1043A SDHC_DAT 4 7 Muxes are used on the board The figure below shows the LS1043A connections for DSPI LS1043A SPI_MOSI SPI_MISO SPI_CLK SPI_CS 0 3 SDHC_DAT 4 7 Leve...

Page 25: ...de Each of these ports can connect to an Ethernet PHY using the MII or RGMII protocol The figure below shows each EC port connected to a Realtek RTL8211FS PHY on the LS1043ARDB LS1043A RTL8211FS RTL82...

Page 26: ...e activity L Link 2 4 1 MII buses The LS1043ARDB has two media independent interface MII management buses EMI1 and EMI2 that are used to control two separate PHY transceiver devices The MII buses are...

Page 27: ...QorIQ LS1043A Reference Manual LS1043ARM for information on supported SerDes combinations The table below lists the SerDes embedded devices used on the LS1043ARDB Table 2 6 LS1043ARDB SerDes embedded...

Page 28: ...ion for LS1043ARDB Table 2 7 LS1043ARDB SerDes1 protocol combination IPD protocol combo hexadecimal SRDS_PRTCL_S1 128 143 RCW hexadecimal A B C D 0F 1455 XFI QSGMII PCIe 2 x1 PCIe 3 x1 The figure belo...

Page 29: ...s J22 2 3 39 Reserved pin 3 3 V 41 Reserved pin 3 3 V 45 Reserved pin VPA 3 3 V 5 0 V 47 Reserved pin VPA 49 Reserved pin VPA 51 Reserved pin VPA 2 6 USB interface The LS1043A processor has three inte...

Page 30: ...ssor has up to four I2C buses most of them are multiplexed pins To simplify the circuit and save many mux demux parts LS1043ARDB attach all devices to I2C1 port The LS1043ARDB I2C has the following fe...

Page 31: ...f of the device is used as an SPD EEPROM for DDR The other half is used as a store system ID and MAC address 0x4C ADT7461 ON Semiconductor Thermal monitor 0x08 PC34VR500V4 Freescale Semiconductor Powe...

Page 32: ...e R W bit as an address member though some datasheets might do so For consistency all I2C addresses are of 7 bits only Chapter 2 Interfaces QorIQ LS1043A Reference Design Board Reference Manual Rev 0...

Page 33: ...I2C interface QorIQ LS1043A Reference Design Board Reference Manual Rev 0 08 2015 32 Freescale Semiconductor Inc...

Page 34: ...peripherals The LS1043ARDB has an onboard CPLD that is used to configure the board for the required functionality for example managing system power and reset sequencing and controlling signal muxing...

Page 35: ...A AQR105 B1 VA 2 1 V 0 5 A LT3085 QSGMII VDD25 2 5 V 1 A DDR4VPP 2 5 V 0 2 A LTC3568 LTM4644 1 2 3 1 2 1 3 3 2 2 1 LTM4649 2 1 0 V 10 A Core VDD DVDD EVDD 3 3 V 4 5 A 1 TVDD 1 2 V 0 1 A OVDD LVDD 1 8...

Page 36: ...ctions Reset signal generation and distribution System reset features are Power on reset POR for the LS1043A processor NOR flash PCIe DDR and PHY devices with initialization of all CPLD registers to t...

Page 37: ...D_B SDHC_WP USB2_DRVVBUS USB2_PWRFAULT and TDM_CLK 9 12 Select SD_DATA 4 7 and SPI_CS 0 3 _B NOR bank selection Split NOR flash into 8 banks 3 3 2 CPLD block diagram The figure below shows a detailed...

Page 38: ...RST_B ETHPHY_RST_B QSGMII_RST_B RST_FLSH_B IFC_CLE cfg_rcw_src 8 SEL 1 2 RTC TA_BB_RTC Figure 3 2 CPLD block diagram 3 3 3 CPLD registers CPLD has a board control and status register BCSR address doma...

Page 39: ...f POR Reset configuration input pins such as CFG_RCW_SRC 0 8 CFG_SVR 0 1 CFG_GPINPUT 0 7 CFG_ENG_USE 0 2 and CFG_DRAM_TYPE function differently when the device is not in the Reset state The LS1043A co...

Page 40: ...G_SOC_USE CFG_GPINPUT 0 3 DRAM type DDR4 or DDR3L CFG_DRAM_TYPE System version register CFG_SVR 0 1 CFG_IFC_TE 5 RCW configuration time Time required varies according to the RCW source and CLKIN frequ...

Page 41: ...system clock CFG_ENG_USE1 IFC_OE_B CFG_ENG_USE2 IFC_WP_0_B CFG_SVR0 IFC_A 16 SW5 8 CFG_SVR1 IFC_A 17 SW5 7 CFG_TEST_SEL TEST_SEL_B SW5 3 CFG_SOC_USE ASLEEP Pullup CFG_DRAM_TYPE IFC_A21 Power down by R...

Page 42: ...ply The LS1043ARDB DDR power supply provides to the DDR4 interface the voltages shown in the table below Table 3 4 DDR supply voltages Voltage name Voltage Current Description GVDD 1 2 V 2 5 A DRAM co...

Page 43: ...SW3 GVDD voltage as VTT An LDO voltage regulator of VR500 generates 50 of GVDD voltage as VREF 3 6 POVDD supply J12 and J13 connectors on the LS1043ARDB connect POVDD power line to LS1043A PROG_MTR an...

Page 44: ...ck frequency selection MPIC controller Temperature anode and cathode 4 1 Clocking scheme The figure below shows the LS1043ARDB clocking scheme NOTE For RDBs Freescale does not support spread spectrum...

Page 45: ...o supports single ended clock source for SYSCLK and DDRCLK Both the differential and single ended system clocks are provided by an IDT 6V49205BNLGI device which is a programmable frequency synthesizer...

Page 46: ...ard interrupt TDMR1 and TDMR2 interrupt 4 4 Temperature anode and cathode The LS1043ARDB has two pins TD1_Anode and TD1_Cathode These pins are connected to a thermal body diode on the die that allows...

Page 47: ...Temperature anode and cathode QorIQ LS1043A Reference Design Board Reference Manual Rev 0 08 2015 46 Freescale Semiconductor Inc...

Page 48: ...ntains the following sections ARM JTAG architecture CMSIS DAP GPIOs 5 1 ARM JTAG architecture The ARM JTAG architecture is shown in the figure below QorIQ LS1043A Reference Design Board Reference Manu...

Page 49: ...LS1043ARDB has a JTAG header J16 that helps the LS1043A processor to communicate externally with CodeWarrior TAP 5 2 CMSIS DAP This section describes the MBED circuit on the LS1043ARDB MBED is an open...

Page 50: ...hich provides a quick and easy mechanism for loading different CMSIS DAP applications such as flash programmers run control debug interfaces serial to USB converters and so on 5 3 GPIOs The LS1043ARDB...

Page 51: ...1_25 TDMA_RSYNC TDM slot IRQ 6 GPIO1_26 TDMA_TXD TDM slot IRQ 7 GPIO1_27 TDMA_TSYNC TDM slot IRQ 8 GPIO1_28 TDMB_RXD TDM slot IRQ 9 GPIO1_29 TDMB_RSYNC TDM slot IRQ 10 GPIO1_30 TDMB_TXD TDM slot IRQ 1...

Page 52: ...G_RCW_SRC1 8 R W See section 6 1 6 55 6 POR RCW source location register 2 CPLD_REG_RCW_SRC2 8 R W See section 6 1 7 56 7 Flash bank selection register CPLD_REG_BANK 8 R W See section 6 1 8 56 8 Syste...

Page 53: ...register to specify CPLD major version Address 0h base 0h offset 0h Bit 0 1 2 3 4 5 6 7 Read VER Reserved Write Reset 0 0 0 0 0 0 0 1 CPLD_VER field descriptions Field Description 0 3 VER CPLD major v...

Page 54: ...escriptions Field Description 0 7 PCBA_VER PCBA version 6 1 4 System reset register CPLD_SYSTEM_RST Write this register to reset the whole system maintaining all CPLD registers current values Address...

Page 55: ...N RCW source location control enable 0 RCW source location control disable default value 1 RCW source location control enable 1 SYSCLK_IN_ CTRL_EN System clock single ended or differential input contr...

Page 56: ...interface control enable 6 FLASH_BANK_ CTRL_EN Flash bank control enable 0 Flash bank control disable default value 1 Flash bank control enable 7 This field is reserved 6 1 6 POR RCW source location...

Page 57: ...OR RCW source location 1 7 This field is reserved 6 1 8 Flash bank selection register CPLD_REG_BANK Use this register to select flash bank Address 0h base 7h offset 7h Bit 0 1 2 3 4 5 6 7 Read BANK_CT...

Page 58: ...N_ SEL System clock input selection 0 System clock differential input 1 System clock single ended input 1 7 This field is reserved 6 1 10 UART1 output selection register CPLD_UART_SEL Use this registe...

Page 59: ...nce clock Address 0h base Ah offset Ah Bit 0 1 2 3 Read SD1REFCLK_SEL Reserved Write Reset 0 0 0 0 Bit 4 5 6 7 Read Reserved Write Reset 0 0 0 0 CPLD_SD1REFCLK_SEL field descriptions Field Description...

Page 60: ...lection 0 TDM_CLK 1 SDHC USB 1 7 This field is reserved 6 1 13 SDHC or SPI_CS selection register CPLD_SDHC_SPICS_SEL Use this register to select SDHC or SPI_CS Address 0h base Ch offset Ch Bit 0 1 2 3...

Page 61: ...s reserved 6 1 15 Global reset register CPLD_GLOBAL_RST Write this register to reset the whole system initializing all CPLD registers to their default values Address 0h base Eh offset Eh Bit 0 1 2 3 4...

Page 62: ...default value 1 7 This field is reserved 6 1 17 RTC clock assignment register CPLD_REG_RTC Use this register to indicate if the RTC clock is assigned to RTC or TA_BB_RTC Address 0h base 10h offset 10h...

Page 63: ...C field descriptions continued Field Description 1 7 This field is reserved CPLD memory map register definitions QorIQ LS1043A Reference Design Board Reference Manual Rev 0 08 2015 62 Freescale Semico...

Page 64: ...provides the revision history of this document Revision number Date Topic cross reference Change description Rev 0 08 2015 Initial public release QorIQ LS1043A Reference Design Board Reference Manual...

Page 65: ...QorIQ LS1043A Reference Design Board Reference Manual Rev 0 08 2015 64 Freescale Semiconductor Inc...

Page 66: ...eters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including typical...

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