CPLD_UART_SEL field descriptions (continued)
Field
Description
0
RJ45
1
CMSIS-DAP (default value)
1–7
-
This field is reserved.
6.1.11 SerDes PLL1 reference clock input selection register
(CPLD_SD1REFCLK_SEL)
Use this register to specify input for the SerDes PLL1 reference clock.
Address: 0h base + Ah offset = Ah
Bit
0
1
2
3
Read
Write
Reset
0
0
0
0
Bit
4
5
6
7
Read
Write
Reset
0
0
0
0
CPLD_SD1REFCLK_SEL field descriptions
Field
Description
0
SD1REFCLK_
SEL
SerDes PLL1 reference clock input selection
0
100 MHz (default value)
1
156.25 MHz
1–7
-
This field is reserved.
CPLD memory map / register definitions
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 0, 08/2015
58
Freescale Semiconductor, Inc.
