• Latch out address lines IFC_ADDR[0:15] from multiplexed data and address
lines
• Read/write CPLD BCSR registers for board configuration
• Multiplexed pin selection:
• Mux SDHC_CD_B, SDHC_WP, USB2_DRVVBUS, USB2_PWRFAULT, and
TDM_CLK[9:12]
• Select SD_DATA[4:7] and SPI_CS[0:3]_B
• NOR bank selection: Split NOR flash into 8 banks.
3.3.2 CPLD block diagram
The figure below shows a detailed block diagram of the CPLD controller on the
LS1043ARDB.
CPLD controller
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 0, 08/2015
36
Freescale Semiconductor, Inc.
