Power up
Power
sequencer
PLD_CLK
Reset
sequencer
POR
sequencer
Address
latcher
BCSR
PLL
25 MHz
POR config switches
(SW4, SW5[1])
IFC_AD[0:15]
IFC_AVD
IFC_ADDR[0:15]
IFC_WE, IFC_OE, IFC_CS
IFC_ADDR[23:27]
TVDD_PG, S1VDD_PG
P5V0_PG, P3V3_PG
POR_B (PMIC PG)
pmic_pwron
RRESET_REQ_B
RST_PLD_N
JTAG_RST_B
RST_REG
RST_PCIE_N
TDMR_RST_N
XGT_RST_B
DDR_RST_B
ETHPHY_RST_B
QSGMII_RST_B
RST_FLSH_B
IFC_CLE (cfg_rcw_src[8])
SEL
1:2
RTC
TA_BB_RTC
Figure 3-2. CPLD block diagram
3.3.3 CPLD registers
CPLD has a board control and status register (BCSR) address domain that contains
registers memory mapped to the LS1043ARDB. These registers can be accessed from
CPLD using IFC. The table below shows the peripheral data bus width and memory map
for CPLD.
Chapter 3 Power Supplies and CPLD Controller
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 0, 08/2015
Freescale Semiconductor, Inc.
37
