Table 3-2. PORESET_B sequence
Step
Sequence stage
Description
1
PORESET_B: General information
1. PORESET_B is asserted.
2. CPLD drives CFG_RCW_SRC[0..8] and all reset configuration
input signals to the LS1043A processor (see
3. CPLD deasserts PORESET_B and the LS1043A processor
samples the configuration pins.
4. The LS1043A processor asserts HRESET_B and loads RCW.
5. After RCW is loaded, the LS1043A processor deasserts
HRESET_B.
2
PORESET_B: During negation
1. The LS1043A processor samples the configuration signals,
and determines the interface to load RCW.
2. The LS1043A processor asserts HRESET_B throughout
PORESET_B.
3
PORESET_B: After negation
The LS1043A processor begins the configuration process and starts
loading RCW.
4
POR configuration input
The reset configuration inputs are sampled to determine:
• Configuration source: CFG_RCW_SRC[0:8]
• CFG_ENG_USE[0:2]
• CFG_SOC_USE
• CFG_GPINPUT[0:3]
• DRAM type (DDR4 or DDR3L): CFG_DRAM_TYPE
• System version register: CFG_SVR[0:1]
• CFG_IFC_TE
5
RCW configuration time
Time required varies according to the RCW source and CLKIN
frequency.
NOTE
The LS1043ARDB has default DIP switch settings that can
manually be repositioned based on the user-selected
configuration levels.
3.4.1 Reset configuration signals
The table below describes the reset configuration input signals on the LS1043ARDB.
Table 3-3. Reset configuration input signals
Configuration signal
Pin location
DIP switch preset
Description
CFG_RCW_SRC0
IFC_CLE
SW4[1]
Specifies RCW fetch location
CFG_RCW_SRC1
IFC_AD8
SW4[2]
Specifies RCW fetch location
CFG_RCW_SRC2
IFC_AD9
SW4[3]
Specifies RCW fetch location
CFG_RCW_SRC3
IFC_AD10
SW4[4]
Specifies RCW fetch location
CFG_RCW_SRC4
IFC_AD11
SW4[5]
Specifies RCW fetch location
CFG_RCW_SRC5
IFC_AD12
SW4[6]
Specifies RCW fetch location
Table continues on the next page...
Chapter 3 Power Supplies and CPLD Controller
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 0, 08/2015
Freescale Semiconductor, Inc.
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