Table 1-3. LS1043ARDB features (continued)
LS1043ARDB feature
Specification
Description
• 100 MHz or 156.25 MHz for PLL1
• 100 MHz for PLL2
RTC
• Supports 32.768 kHz for RTC or TA_BB_RTC
Power
One dedicated programmable
regulator supplying the LS1043A core
and DDR power domains.
Power supply details for the LS1043ARDB are given
below:
• 1.0 V for core VDD and USB SVDD
• 1.2 V for GVDD
• 1.8 V for LS1043A PROG_SFP and
PROG_MTR (POVDD)
• 1.8 V and 3.3 V for CPLD
• 1.35 V for XVDD
• 1.0 V for SVDD
• 1.8 V for LS1043A general I/O
• 3.3 V for UART/I2C
• 3.3 V for USB HVDD
• 0.6 V for DDR4 VTT/VREF
• 3.3 V / 1.8 V for eSDHC
• 1.0 V for security monitor (VDD_LP)
1.4 Block diagrams
The figure below shows the LS1043A processor block diagram.
Block diagrams
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 0, 08/2015
12
Freescale Semiconductor, Inc.
