Freescale Semiconductor QorIQ LS1043A, Reference Manual

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6.1.7 POR RCW source location register 2
(CPLD_REG_RCW_SRC2)
Use this register to configure RCW source bit 8.
Address: 0h base + 6h offset = 6h
Bit 0 1 2 3 4 5 6 7
Read CFG_RCW_
SRC[8]
Reserved
Write
Reset
0 0 0 0 0 0 0 0
CPLD_REG_RCW_SRC2 field descriptions
Field Description
0
CFG_RCW_
SRC[8]
POR RCW source location
1–7
-
This field is reserved.
6.1.8 Flash bank selection register (CPLD_REG_BANK)
Use this register to select flash bank.
Address: 0h base + 7h offset = 7h
Bit 0 1 2 3 4 5 6 7
Read
BANK_CTRL Reserved
Write
Reset 0 0 0 0 0 0 0 0
CPLD_REG_BANK field descriptions
Field Description
0–2
BANK_CTRL
Bank control bits
3–7
-
This field is reserved.
CPLD memory map / register definitions
QorIQ LS1043A Reference Design Board Reference Manual, Rev. 0, 08/2015
56 Freescale Semiconductor, Inc.