MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
86
Freescale Semiconductor
Clocking
Figure 55
shows the internal distribution of clocks within the MPC8358E.
Figure 55. MPC8358E Clock Subsystem
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. Note that in PCI host mode, the primary
clock input also depends on whether PCI clock outputs are selected with RCWH[PCICKDRV]. When the
device is configured as a PCI host device (RCWH[PCIHOST] = 1) and PCI clock output is selected
(RCWH[PCICKDRV] = 1), CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (
÷
2)
and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration
input selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The
OCCR[PCIOENn] parameters enable the PCI_CLK_OUTn, respectively.
Core PLL
System
LBIU
LSYNC_IN
LSYNC_OUT
LCLK[0:2]
core_clk
e300 Core
csb_clk to Rest
CLKIN
csb_clk
MPC8358E
Local Bus
PCI_CLK_OUT[0:2]
PCI_SYNC_OUT
PCI_CLK/
Clock
Unit
of the Device
lb_clk
CFG_CLKIN_DIV
PCI Clock
PCI_SYNC_IN
Memory
Device
/n
DLL
Divider
MEMC1_MCK[0:5]
MEMC1_MCK[0:5]
DDRC
/2
ddr1_clk
DDRC
Memory
Device
PLL
QUICC
PLL
ce_clk to QUICC Engine Block
Engine