MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
64
Freescale Semiconductor
HDLC, BISYNC, Transparent, and Synchronous UART
Figure 48
shows the UTOPIA timing with internal clock.
Figure 48. UTOPIA AC Timing (Internal Clock) Diagram
19 HDLC, BISYNC, Transparent, and Synchronous
UART
This section describes the DC and AC electrical specifications for the high level data link control (HDLC),
BISYNC, transparent, and synchronous UART protocols of the MPC8360E/58E.
19.1
HDLC, BISYNC, Transparent, and Synchronous UART DC
Electrical Characteristics
Table 61
provides the DC electrical characteristics for the device HDLC, BISYNC, transparent, and
synchronous UART protocols.
Table 61. HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
V
OH
I
OH
= –2.0 mA
2.4
—
V
Output low voltage
V
OL
I
OL
= 3.2 mA
—
0.5
V
Input high voltage
V
IH
—
2.0
OV
DD
+ 0.3
V
Input low voltage
V
IL
—
–0.3
0.8
V
Input current
I
IN
0 V
≤
V
IN
≤
OV
DD
—
±10
μ
A
UtopiaCLK (Output)
t
UIIXKH
t
UIKHOV
Input Signals:
UTOPIA
Output Signals:
UTOPIA
t
UIIVKH
t
UIKHOX