MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
70
Freescale Semiconductor
Package and Pin Listings
21.3
Pinout Listings
Refer to AN3097, “MPC8360/MPC8358E PowerQUICC Design Checklist,” for proper pin termination
and usage.
Table 66
shows the pin list of the MPC8360E TBGA package.
Table 66. MPC8360E TBGA Pinout Listing
Signal
Package Pin Number
Pin Type
Power
Supply
Notes
Primary DDR SDRAM Memory Controller Interface
MEMC1_MDQ[0:31]
AJ34, AK33, AL33, AL35, AJ33, AK34, AK32,
AM36, AN37, AN35, AR34, AT34, AP37, AP36,
AR36, AT35, AP34, AR32, AP32, AM31, AN33,
AM34, AM33, AM30, AP31, AM27, AR30, AT32,
AN29, AP29, AN27, AR29
I/O
GV
DD
—
MEMC1_MDQ[32:63]/
MEMC2_MDQ[0:31]
AN8, AN7, AM8, AM6, AP9, AN9, AT7, AP7, AU6,
AP6, AR4, AR3, AT6, AT5, AR5, AT3, AP4, AM5,
AP3, AN3, AN5, AL5, AN4, AM2, AL2, AH5, AK3,
AJ2, AJ3, AH4, AK4, AH3
I/O
GV
DD
—
MEMC1_MECC[0:4]/
MSRCID[0:4]
AP24, AN22, AM19, AN19, AM24
I/O
GV
DD
—
MEMC1_MECC[5]/
MDVAL
AM23
I/O
GV
DD
—
MEMC1_MECC[6:7]
AM22, AN18
I/O
GV
DD
—
MEMC1_MDM[0:3]
AL36, AN34, AP33, AN28
O
GV
DD
—
MEMC1_MDM[4:7]/
MEMC2_MDM[0:3]
AT9, AU4, AM3, AJ6
O
GV
DD
—
MEMC1_MDM[8]
AP27
O
GV
DD
—
MEMC1_MDQS[0:3]
AK35, AP35, AN31, AM26
I/O
GV
DD
—
MEMC1_MDQS[4:7]/
MEMC2_MDQS[0:3]
AT8, AU3, AL4, AJ5
I/O
GV
DD
—
MEMC1_MDQS[8]
AP26
I/O
GV
DD
—
MEMC1_MBA[0:1]
AU29, AU30
O
GV
DD
—
MEMC1_MBA[2]
AT30
O
GV
DD
—
MEMC1_MA[0:14]
AU21, AP22, AP21, AT21, AU25, AU26, AT23,
AR26, AU24, AR23, AR28, AU23, AR22, AU20,
AR18
O
GV
DD
—
MEMC1_MODT[0:1]
AG33, AJ36
O
GV
DD
6
MEMC1_MODT[2:3]/
MEMC2_MODT[0:1]
AT1, AK2
O
GV
DD
6
MEMC1_MWE
AT26
O
GV
DD
—
MEMC1_MRAS
AT29
O
GV
DD
—
MEMC1_MCAS
AT24
O
GV
DD
—
MEMC1_MCS[0:1]
AU27, AT27
O
GV
DD
—