MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Freescale Semiconductor
51
JTAG
Figure 33
provides the test access port timing diagram.
Figure 33. Test Access Port Timing Diagram
VM = Midpoint Voltage (OVDD/2)
VM
VM
t
JTIVKH
t
JTIXKH
JTAG
External Clock
Output Data Valid
t
JTKLOX
t
JTKLOZ
t
JTKLOV
Input
Data Valid
Output Data Valid
TDI, TMS
TDO
TDO