Freescale Semiconductor MPC8358E Hardware Specificftion Download Page 49

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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor

JTAG

10.2

JTAG AC Electrical Characteristics

This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the device.

Table 43

provides the JTAG AC timing specifications as defined in

Figure 30

through

Figure 33

Table 43. JTAG AC Timing Specifications (Independent of CLKIN)

At recommended operating conditions (see

Table 2

Parameter

Symbol

Min

Max

Unit

Notes

JTAG external clock frequency of operation

JTG

33.3

MHz

—

JTAG external clock cycle time

JTG

—

JTAG external clock duty cycle

JTKHKL

JTG

—

JTAG external clock rise and fall times

JTGR

& t

JTGF

—

TRST assert time

TRST

—

Input setup times:

Boundary-scan data

TMS, TDI

JTDVKH

JTIVKH

4
4

—
—

Input hold times:

Boundary-scan data

TMS, TDI

JTDXKH

JTIXKH

10
10

—
—

Valid times:

Boundary-scan data

TDO

JTKLDV

JTKLOV

2
2

11
11

Output hold times:

Boundary-scan data

TDO

JTKLDX

JTKLOX

2
2

—
—

JTAG external clock to output high impedance:

Boundary-scan data

TDO

JTKLDZ

JTKLOZ

2
2

5, 6

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of t

TCLK

to the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50-

load (see

Figure 22

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

JTDVKH

symbolizes JTAG

device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t

JTG

clock

reference (K) going to the high (H) state or setup time. Also, t

JTDXKH

symbolizes JTAG timing (JT) with respect to the time

data input signals (D) went invalid (X) relative to the t

JTG

clock reference (K) going to the high (H) state. Note that, in general,

the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t

TCLK

5. Non-JTAG signal output timing with respect to t

TCLK

6. Guaranteed by design and characterization.

Summary of Contents for MPC8358E

Page 1: ...ol plane and also has data plane functionality For functional characteristics of the processor refer to the MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual Rev 3...

Page 2: ...tition system parameters and data in an extremely efficient way such as using one 32 bit DDR memory controller for control plane processing and the other for data plane processing The MPC8358E has a s...

Page 3: ...ower Architecture technology QUICC Engine unit Two 32 bit RISC controllers for flexible support of the communications peripherals each operating up to 500 MHz for the MPC8360E and 400 MHz for the MPC8...

Page 4: ...cuit emulation service CES 2 0 in accordance with ITU T I 163 1 and ATM Forum af vtoa 00 0078 000 IMA Inverse Multiplexing over ATM for up to 31 IMA links over 8 IMA groups in accordance with the ATM...

Page 5: ...358E with 1 bit mode for E3 T3 rates in clear channel Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC and MCC serial channels MCC is only available on the...

Page 6: ...RAM memory controllers on the MPC8360E and a single DDR SDRAM memory controller on the MPC8358E Programmable timing supporting both DDR1 and DDR2 SDRAM On the MPC8360E the DDR buses can be configured...

Page 7: ...iguration registers accessible from PCI Local bus controller LBC Multiplexed 32 bit address and data operating at up to 133 MHz Eight chip selects support eight external slaves Up to eight beat burst...

Page 8: ...n completed segment and chain DMA external handshake signals DMA_DREQ 0 3 DMA_DACK 0 3 DMA_DONE 0 3 There is one set for each DMA channel The pins are multiplexed to the parallel IO pins with other QE...

Page 9: ...VIN 0 3 to GVDD 0 3 V 2 5 DDR DRAM reference MVREF 0 3 to GVDD 0 3 V 2 5 Three speed Ethernet signals LVIN 0 3 to LVDD 0 3 V 4 5 Local bus DUART CLKIN system control and power management I2 C SPI and...

Page 10: ...module frequencies 500 MHz and e300 frequencies 667 MHz For a QUICC Engine module frequency of 500 MHz or an e300 frequency of 667 MHz AVDD 1 2 V 60 mV 1 3 V 50 mV V 1 DDR and DDR2 DRAM I O supply vol...

Page 11: ...shows the undershoot and overshoot voltage of the PCI interface of the device for the 3 3 V signals respectively Figure 4 Maximum AC Waveforms on PCI interface for 3 3 V Signaling GND GND 0 3 V GND 0...

Page 12: ...pins will actively be driven and cause contention and excessive current In order to avoid actively driving the I O pins and to eliminate excessive current draw apply the core voltage VDD before the I...

Page 13: ...re the core supply voltage and I O supply voltages to be powered down in any particular order 3 Power Characteristics The estimated typical power dissipation values are shown in Table 4 and Table 5 Ta...

Page 14: ...chmark application 7 Maximum power is based on a voltage of VDD 1 3 V for applications that use 667 MHz CPU or 500 QE with WC process a junction TJ 70 C and an artificial smoke test 8 This frequency c...

Page 15: ...Estimated Typical I O Power Dissipation Interface Parameter GVDD 1 8 V GVDD 2 5 V OVDD 3 3 V LVDD 3 3 V LVDD 2 5 V Unit Comments DDR I O 65 utilization Rs 20 Rt 50 2 pairs of clocks 200 MHz 1 32 bits...

Page 16: ...VIN 0 5V or OVDD 0 5V VIN OVDD IIN 10 A PCI_SYNC_IN input current 0 5 V VIN OVDD 0 5 V IIN 100 A Table 8 CLKIN AC Timing Specifications Parameter Condition Symbol Min Typical Max Unit Notes CLKIN PCI_...

Page 17: ...rise and fall time LVDD 2 5 V LVDD 3 3 V tG125R tG125F 0 75 1 0 ns 1 GTX_CLK125 duty cycle GMII TBI 1000Base T for RGMII RTBI tG125H tG125 45 47 55 53 2 GTX_CLK125 jitter 150 ps 2 Notes 1 Rise and fal...

Page 18: ...time for POR config signals CFG_RESET_SOURCE 0 2 and CFG_CLKIN_DIV with respect to negation of PORESET when the device is in PCI host mode 4 tCLKIN 2 Input setup time for POR config signals CFG_RESET_...

Page 19: ...CC Engine block I O frequencies and the minimal QUICC Engine block core frequency for each interface Table 12 PLL and DLL Lock Times Parameter Condition Min Max Unit Notes PLL lock times 100 s DLL loc...

Page 20: ...interface operating frequency 3 The bit rate limit is independent of the data bus width that is the same for serial nibble or octal interfaces 4 TDM in high speed mode for serial data interface Table...

Page 21: ...is parameter is sampled GVDD 1 8 V 0 090 V f 1 MHz TA 25 C VOUT GVDD 2 VOUT peak to peak 0 2 V Table 16 DDR SDRAM DC Electrical Characteristics for GVDD typ 2 5 V Parameter Condition Symbol Min Max Un...

Page 22: ...typ 2 5 V Parameter Condition Symbol Min Max Unit Notes Input output capacitance DQ DQS CIO 6 8 pF 1 Delta input output capacitance DQ DQS CDIO 0 5 pF 1 Note 1 This parameter is sampled GVDD 2 5 V 0 1...

Page 23: ...Parameter Symbol Min Max Unit Notes MDQS MDQ MECC input skew per byte 333 MHz 266 MHz 200 MHz tDISKEW 750 1125 1250 750 1125 1250 ps 1 2 Notes 1 AC timing values are based on the DDR data rate which...

Page 24: ...tDDKHCS 2 1 2 8 3 5 ns 4 MCS n output hold with respect to MCK 333 MHz 266 MHz 200 MHz tDDKHCX 2 0 2 7 3 5 ns 4 MCK to MDQS tDDKHMH 0 8 0 7 ns 5 9 MDQ MECC MDM output setup with respect to MDQS 333 MH...

Page 25: ...ol register is set to adjust the memory clocks by applied cycle 5 Note that tDDKHMH follows the symbol conventions described in note 1 For example tDDKHMH describes the DDR timing DD from the rising e...

Page 26: ...7 Timing Diagram for tAOSKEW Measurement Figure 8 provides the AC test load for the DDR bus Figure 8 DDR AC Test Load Table 22 DDR and DDR2 SDRAM Measurement Conditions Symbol DDR DDR2 Unit Notes VTH...

Page 27: ...ble 23 provides the DC electrical characteristics for the DUART interface of the device Table 23 DUART DC Electrical Characteristics Parameter Symbol Min Max Unit Notes High level input voltage VIH 2...

Page 28: ...he Hewlett Packard reduced pin count interface for Gigabit Ethernet Physical Layer Device Specification Version 1 2a 9 22 2000 The electrical characteristics for the MDIO and MDC are specified in Sect...

Page 29: ...low voltage VOL IOL 4 0 mA LVDD Min GND 0 50 V Input high voltage VIH 2 0 LVDD 0 3 V Input low voltage VIL 0 3 0 90 V Input current IIN 0 V VIN LVDD 10 A Note 1 GMII MII pins that are not needed for...

Page 30: ...tate H relative to the time date input signals D going invalid X or hold time Note that in general the clock reference symbol representation is based on three letters representing the clock of a parti...

Page 31: ...MII receive timing GR with respect to the time data input signals D went invalid X relative to the tGRX clock reference K going to the low L state or hold time Note that in general the clock reference...

Page 32: ...going high H until data outputs D are invalid X Note that in general the clock reference symbol representation is based on two to three letters representing the clock of a particular functional For ex...

Page 33: ...the time data input signals D reach the valid state V relative to the tMRX clock reference K going to the high H state or setup time Also tMRDXKL symbolizes MII receive timing GR with respect to the t...

Page 34: ...5 65 REF_CLK to RMII data TXD 1 0 TX_EN delay tRMTKHDX tRMTKHDV 2 10 ns REF_CLK data clock rise time tRMXR 1 0 4 0 ns REF_CLK data clock fall time tRMXF 1 0 4 0 ns Note 1 The symbols used for timing s...

Page 35: ...0 4 0 ns Note 1 The symbols used for timing specifications follow the pattern of t first three letters of functional block signal state reference state for inputs and t first two letters of functional...

Page 36: ...symbols used for timing specifications follow the pattern of t first two letters of functional block signal state reference state for inputs and t first two letters of functional block reference state...

Page 37: ...al state reference state for inputs and t first two letters of functional block reference state signal state for outputs For example tTRDVKH symbolizes TBI receive timing TR with respect to the time d...

Page 38: ...k Note also that the notation for rise R and fall F times follows the clock symbol that is being represented For symbols representing skews the subscript is skew SK followed by the clock that is being...

Page 39: ...Controller 10 100 1000 Mbps GMII MII RMII TBI RGMII RTBI Electrical Characteristics 8 3 1 MII Management DC Electrical Characteristics The MDC and MDIO are defined to operate at a supply voltage of 3...

Page 40: ...gnal state reference state for inputs and t first two letters of functional block reference state signal state for outputs For example tMDKHDX symbolizes management data timing MD for the time tMDC fr...

Page 41: ...MPC8360E 58E Table 38 IEEE 1588 Timer AC Specifications Parameter Symbol Min Max Unit Notes Timer clock frequency tTMRCK 0 70 MHz 1 Input setup to timer clock tTMRCKS 2 3 Input hold from timer clock t...

Page 42: ...ed Parameter Symbol1 Min Max Unit Notes Local bus cycle time tLBK 7 5 ns 2 Input setup to local bus clock except LUPWAIT tLBIVKH1 1 7 ns 3 4 LUPWAIT input setup to local bus clock tLBIVKH2 1 9 ns 3 4...

Page 43: ...nput timings are measured at the pin 5 tLBOTOT1 should be used when RCWH LALE is not set and when the load on LALE output pin is at least 10 pF less than the load on LAD output pins 6 tLBOTOT2 should...

Page 44: ...of LCLK0 for all outputs and for LGTA and LUPWAIT inputs or rising edge of LCLK0 for all other inputs 3 All signals are measured from OVDD 2 of the rising falling edge of LCLK0 to 0 4 OVDD of the sign...

Page 45: ...Signals LA 27 31 LBCTL LBCKE LOE LSDA10 LSDWE LSDRAS LSDCAS LSDDQM 0 3 tLBKHOV tLBKHOV tLBKHOV LSYNC_IN Input Signals LAD 0 31 LDP 0 3 Output Data Signals LAD 0 31 LDP 0 3 Output Address Signal LAD 0...

Page 46: ...ypass Mode LSYNC_IN UPM Mode Input Signal LUPWAIT tLBIXKH2 tLBIVKH2 tLBIVKH1 tLBIXKH1 tLBKHOZ1 T1 T3 Input Signals LAD 0 31 LDP 0 3 UPM Mode Output Signals LCS 0 3 LBS 0 3 LGPL 0 5 GPCM Mode Output Si...

Page 47: ...cal Bus Figure 27 Local Bus Signals GPCM UPM Signals for LCRR CLKDIV 4 DLL Bypass Mode LCLK UPM Mode Input Signal LUPWAIT tLBIXKH tLBIVKH tLBIVKH tLBIXKH tLBKHOZ T1 T3 UPM Mode Output Signals LCS 0 3...

Page 48: ...stics for the IEEE 1149 1 JTAG interface of the device Table 42 JTAG interface DC Electrical Characteristics Characteristic Symbol Condition Min Max Unit Output high voltage VOH IOH 6 0 mA 2 4 V Outpu...

Page 49: ...idpoint voltage of the falling rising edge of tTCLK to the midpoint of the signal in question The output timings are measured at the pins All output timings assume a purely resistive 50 load see Figur...

Page 50: ...nput Timing Diagram Figure 31 provides the TRST timing diagram Figure 31 TRST Timing Diagram Figure 32 provides the boundary scan timing diagram Figure 32 Boundary Scan Timing Diagram Output Z0 50 OVD...

Page 51: ...Rev 4 Freescale Semiconductor 51 JTAG Figure 33 provides the test access port timing diagram Figure 33 Test Access Port Timing Diagram VM Midpoint Voltage OVDD 2 VM VM tJTIVKH tJTIXKH JTAG External Cl...

Page 52: ...to VIL max with a bus capacitance from 10 to 400 pF tI2KLKV 20 0 1 CB 250 ns 2 Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns 3 Capacitance for each I O pin CI 10 p...

Page 53: ...s I2 C timing I2 with respect to the time data input signals D reach the valid state V relative to the tI2C clock reference K going to the high H state or setup time Also tI2SXKL symbolizes I2 C timin...

Page 54: ...rameter Symbol1 Min Max Unit Notes Clock to output valid tPCKHOV 6 0 ns 2 5 Output hold from clock tPCKHOX 1 ns 2 Clock to output high impedance tPCKHOZ 14 ns 2 3 Input setup to clock tPCIVKH 3 0 ns 2...

Page 55: ...e for inputs and t first two letters of functional block reference state signal state for outputs For example tPCIVKH symbolizes PCI timing PC with respect to the time the input signals I reach the va...

Page 56: ...tics Characteristic Symbol Condition Min Max Unit Output high voltage VOH IOH 6 0 mA 2 4 V Output low voltage VOL IOL 6 0 mA 0 5 V Output low voltage VOL IOL 3 2 mA 0 4 V Input high voltage VIH 2 0 OV...

Page 57: ...Output high voltage VOH IOH 6 0 mA 2 4 V 1 Output low voltage VOL IOL 6 0 mA 0 5 V 1 Output low voltage VOL IOL 3 2 mA 0 4 V 1 Input high voltage VIH 2 0 OVDD 0 3 V 1 Input low voltage VIL 0 3 0 8 V I...

Page 58: ...Symbol Condition Min Max Unit Input high voltage VIH 2 0 OVDD 0 3 V Input low voltage VIL 0 3 0 8 V Input current IIN 10 A Output low voltage VOL IOL 6 0 mA 0 5 V Output low voltage VOL IOL 3 2 mA 0 4...

Page 59: ...ol2 Min Max Unit SPI outputs Master mode internal clock delay tNIKHOX tNIKHOV 0 3 8 ns SPI outputs Slave mode external clock delay tNEKHOX tNEKHOV 2 8 ns SPI inputs Master mode internal clock input se...

Page 60: ...e Internal Clock Diagram 17 TDM SI This section describes the DC and AC electrical specifications for the time division multiplexed and serial interface of the MPC8360E 58E 17 1 TDM SI DC Electrical C...

Page 61: ...SI inputs External clock input setup time tSEIVKH 5 ns TDM SI inputs External clock input hold time tSEIXKH 2 ns Notes 1 Output specifications are measured from the 50 level of the rising edge of CLK...

Page 62: ...timing specifications Table 59 UTOPIA DC Electrical Characteristics Characteristic Symbol Condition Min Max Unit Output high voltage VOH IOH 8 0 mA 2 4 V Output low voltage VOL IOL 8 0 mA 0 5 V Input...

Page 63: ...ld time tUEIXKH 1 ns 3 Notes 1 Output specifications are measured from the 50 level of the rising edge of CLKIN to the 50 level of the signal Timings are measured at the pin 2 The symbols used for tim...

Page 64: ...ynchronous UART protocols of the MPC8360E 58E 19 1 HDLC BISYNC Transparent and Synchronous UART DC Electrical Characteristics Table 61 provides the DC electrical characteristics for the device HDLC BI...

Page 65: ...l block signal state reference state for inputs and t first two letters of functional block reference state signal state for outputs For example tHIKHOX symbolizes the outputs internal timing HI for t...

Page 66: ...rence the rising edge of the clock these AC timing diagrams also apply when the falling edge is the active edge Figure 50 shows the timing with external clock Figure 50 AC Timing External Clock Diagra...

Page 67: ...Low level output voltage IOL 100 A VOL 0 2 V Input current IIN 10 A Table 65 USB General Timing Parameters Parameter Symbol1 Min Max Unit Notes USB clock cycle time tUSCK 20 83 ns Full speed 48 MHz US...

Page 68: ...n 21 1 Package Parameters for the TBGA Package and Section 21 2 Mechanical Dimensions of the TBGA Package for information on the package 21 1 Package Parameters for the TBGA Package The package parame...

Page 69: ...Rev 4 Freescale Semiconductor 69 Package and Pin Listings 21 2 Mechanical Dimensions of the TBGA Package Figure 53 depicts the mechanical dimensions and bottom surface nomenclature of the device 740 T...

Page 70: ...Q 32 63 MEMC2_MDQ 0 31 AN8 AN7 AM8 AM6 AP9 AN9 AT7 AP7 AU6 AP6 AR4 AR3 AT6 AT5 AR5 AT3 AP4 AM5 AP3 AN3 AN5 AL5 AN4 AM2 AL2 AH5 AK3 AJ2 AJ3 AH4 AK4 AH3 I O GVDD MEMC1_MECC 0 4 MSRCID 0 4 AP24 AN22 AM19...

Page 71: ...7 AP13 AP15 AN13 I O GVDD MEMC2_MBA 0 2 AU12 AU15 AU13 O GVDD MEMC2_MA 0 14 AT12 AP11 AT13 AT14 AR13 AR15 AR16 AT16 AT18 AT17 AP10 AR20 AR17 AR14 AR11 O GVDD MEMC2_MWE AU10 O GVDD MEMC2_MRAS AT11 O GV...

Page 72: ...O OVDD Local Bus Controller Interface LAD 0 31 N32 N33 N35 N36 P37 P32 P34 R36 R35 R34 R33 T37 T35 T34 T33 U37 T32 U36 U34 V36 V35 W37 W35 V33 V32 W34 Y36 W32 AA37 Y33 AA35 AA34 I O OVDD LDP 0 CKSTOP...

Page 73: ...6 CKSTOP_OUT E35 I O OVDD IRQ 7 LCS 7 CKSTOP_IN H36 I O OVDD DUART UART1_SOUT M1SRCID 0 M2SRCID 0 LSRCID 0 E32 O OVDD UART1_SIN M1SRCID 1 M2SRCID 1 LSRCID 1 B34 I O OVDD UART1_CTS M1SRCID 2 M2SRCID 2...

Page 74: ...CE_PC 7 C19 I O LVDD2 CE_PC 8 9 A4 C5 I O LVDD0 CE_PC 10 30 T5 T4 T2 T1 R5 R3 R1 C11 D12 F13 B10 C10 E12 A9 B8 D10 A14 E15 B14 D15 AH2 I O OVDD CE_PD 0 27 E11 D9 C8 F11 A7 E9 C7 A6 F10 B6 D7 E8 B5 A5...

Page 75: ...B24 B27 B30 C4 C6 C9 C15 C26 C32 D3 D8 D11 D14 D17 D19 D23 D27 E7 E13 E25 E30 E36 F4 F37 G34 H1 H5 H32 H33 J4 J32 J37 K1 L3 L5 L33 L34 M1 M34 M35 N37 P2 P5 P35 P36 R4 T3 U1 U5 U35 V37 W1 W4 W33 W36 Y3...

Page 76: ...F29 F31 F32 F33 G6 J6 K32 M32 N6 P33 R6 R32 U32 V6 Y5 Y32 AB6 AB33 AD6 AF32 AK6 AL6 AM7 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM18 AM21 AM25 AM28 AM32 AN15 AN21 AN26 AU9 AU17 Power for core 1 2 V VDD OVD...

Page 77: ...mily Reference Manual section on RGMII Pins for information about the two UCC2 Ethernet interface options 10 It is recommended that MDIC0 be tied to GND using an 18 2 resistor and MDIC1 be tied to DDR...

Page 78: ...E23 A26 I O OVDD PCI_AD 24 CE_PG 24 B21 I O LVDD2 PCI_AD 23 0 CE_PG 23 0 C24 C25 D25 B25 E24 F24 A27 A28 F27 A30 C30 D30 E29 B31 C31 D31 D32 A32 C33 B33 F30 E31 A34 D33 I O OVDD PCI_C BE 3 0 CE_PF 10...

Page 79: ...C37 AA32 AC36 AC34 AD36 O OVDD LCS 0 5 AD33 AG37 AF34 AE33 AD32 AH37 O OVDD LWE 0 3 LSDDQM 0 3 LBS 0 3 AG35 AG34 AH36 AE32 O OVDD LBCTL AD35 O OVDD LALE M37 O OVDD LGPL0 LSDA10 cfg_reset_source0 AB32...

Page 80: ...ART1_RTS M1SRCID 3 M2SRCID 3 LSRCID 3 A35 O OVDD I2C Interface IIC1_SDA D34 I O OVDD 2 IIC1_SCL B35 I O OVDD 2 IIC2_SDA E33 I O OVDD 2 IIC2_SCL C35 I O OVDD 2 QUICC Engine CE_PA 0 F8 I O LVDD0 CE_PA 1...

Page 81: ...27 E11 D9 C8 F11 A7 E9 C7 A6 F10 B6 D7 E8 B5 A5 C2 E4 F5 B1 D2 G5 D1 E2 H6 F3 E1 F2 G3 H4 I O OVDD CE_PE 0 31 K3 J2 F1 G2 J5 H3 G1 H2 K6 J3 K5 K4 L6 P6 P4 P3 P1 N4 N5 N2 N1 M2 M3 M5 M6 L1 L2 L4 E14 C...

Page 82: ...25 E30 E36 F4 F37 G34 H1 H5 H32 H33 J4 J32 J37 K1 L3 L5 L33 L34 M1 M34 M35 N37 P2 P5 P35 P36 R4 T3 U1 U5 U35 V37 W1 W4 W33 W36 Y34 AA3 AA5 AC3 AC32 AC35 AD1 AD37 AE4 AE34 AE36 AF33 AG4 AG6 AG32 AH35 A...

Page 83: ...6 P33 R6 R32 U32 V6 Y5 Y32 AB6 AB33 AD6 AF32 AK6 AL6 AM7 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM18 AM21 AM25 AM28 AM32 AN15 AN21 AN26 AU9 AU17 Power for core 1 2 V VDD OVDD A10 B9 B15 B32 C1 C12 C22 C29...

Page 84: ...These JTAG pins have weak internal pull up P FETs that are always enabled 5 This pin should have a weak pull up if the chip is in PCI host mode Follow PCI specifications recommendation 6 These are On...

Page 85: ...em Core PLL System DDRC2 LBIU LSYNC_IN LSYNC_OUT LCLK 0 2 MEMC2_MCK 0 1 MEMC2_MCK 0 1 core_clk e300 Core csb_clk to Rest CLKIN csb_clk MPC8360E DDRC2 Memory Local Bus PCI_CLK_OUT 0 2 PCI_SYNC_OUT PCI_...

Page 86: ...ured as a PCI host device RCWH PCIHOST 1 and PCI clock output is selected RCWH PCICKDRV 1 CLKIN is its primary input clock CLKIN feeds the PCI clock divider 2 and the multiplexors for PCI_SYNC_OUT and...

Page 87: ...de CFG_CLKIN_DIV must be pulled down low so PCI_SYNC_IN 1 CFG_CLKIN_DIV is the PCI_CLK frequency The csb_clk serves as the clock input to the e300 core A second PLL inside the e300 core multiplies up...

Page 88: ..._clk 3 Off csb_clk1 csb_clk 2 csb_clk 3 1 With limitation only for slow csb_clk rates up to 166 MHz PCI and DMA complex csb_clk Off csb_clk Table 69 Operating Frequencies for the TBGA Package Characte...

Page 89: ...he system PLL The RCWL SVCOD denotes the system PLL VCO internal frequency as shown in Table 71 NOTE The VCO divider must be set properly so that the system VCO frequency is in the range of 600 1400 M...

Page 90: ...between the primary clock input CLKIN or PCI_CLK and the internal coherent system bus clock csb_clk Table 72 shows the expected frequency values for the CSB frequency for select csb_clk to CLKIN PCI_...

Page 91: ...0 14 1 High 1111 15 1 High 0000 16 1 1 CFG_CLKIN_DIV is only used for host mode CLKIN must be tied low and CFG_CLKIN_DIV must be pulled down low in agent mode 2 CLKIN is the input clock in host mode P...

Page 92: ...The QUICC Engine block PLL is controlled by the RCWL CEPMF RCWL CEPDF and RCWL CEVCOD parameters Table 74 shows the multiplication factor encodings for the QUICC Engine block PLL 11 0001 1 1 5 1 8 00...

Page 93: ...0 0 12 01101 0 13 01110 0 14 01111 0 15 10000 0 16 10001 0 17 10010 0 18 10011 0 19 10100 0 20 10101 0 21 10110 0 22 10111 0 23 11000 0 24 11001 0 25 11010 0 26 11011 0 27 11100 0 28 11101 0 29 11110...

Page 94: ...d QUICC Engine block frequencies should be selected according to the performance requirements The QUICC Engine block VCO frequency is derived from the following equations ce_clk primary clock input CE...

Page 95: ...combination of clock domains setting with same input clock are valid Refer to Section 22 Clocking for the appropriate operating frequencies for your device Table 76 Suggested PLL Configurations Conf N...

Page 96: ...tively c5 10000 0 33 533 c6 10001 0 33 566 66 MHz CLKIN PCI_SYNC_IN Options s1h 0011 0000110 66 200 400 s2h 0011 0000101 66 200 500 s3h 0011 0000110 66 200 600 s4h 0100 0000011 66 266 400 s5h 0100 000...

Page 97: ...ions of the MPC8360E 58E 23 1 Thermal Characteristics Table 77 provides the package thermal characteristics for the 37 5 mm 37 5 mm 740 TBGA package Index SPMF CORE PLL CEPMF CEPDF Input Clock MHz CSB...

Page 98: ...ot be adequately predicted from the junction to ambient thermal resistance The thermal performance of any component is strongly dependent on the power dissipation of surrounding components In addition...

Page 99: ...are available the Thermal Characterization Parameter JT can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the followi...

Page 100: ...nt thermal resistance for TBGA package Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction...

Page 101: ...Millennium Electronics MEI 408 436 8770 Loroco Sites 671 East Brokaw Road San Jose CA 95112 Internet www mei millennium com Tyco Electronics 800 522 6752 Chip Coolers P O Box 3668 Harrisburg PA 17105...

Page 102: ...23 3 1 Experimental Determination of the Junction Temperature with a Heat Sink When heat sink is used the junction temperature is determined from a thermocouple inserted at the interface between the...

Page 103: ...on from one PLL to the other is reduced This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range It should be built with surface mount capacitors wi...

Page 104: ...TPS tantalum or Sanyo OSCON 24 4 Connection Recommendations To ensure reliable operation it is highly recommended to connect unused inputs to an appropriate signal level Unused active low inputs shou...

Page 105: ...e driver impedance are targeted at minimum VDD nominal OVDD 105 C 24 6 Configuration Pin Muxing The device provides the user with power on configuration options that can be set through the use of exte...

Page 106: ...on conditions Each part number also contains a revision code that refers to the die mask revision number Table 80 Part Numbering Nomenclature1 1 Not all processor platform and QUICC Engine block frequ...

Page 107: ...watermark Updated the title of Table 19 DDR SDRAM Input AC Timing Specifications In Table 20 DDR and DDR2 SDRAM Input AC Timing Specifications Mode changed table subtitle In Table 27 Table 30 and Tabl...

Page 108: ...fy and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out...

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