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Freescale Semiconductor MPC8250, Family Reference Manual

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Fast Communications Controllers (FCCs)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

29-6

Freescale Semiconductor

 

8

CTSS

CTS sampling
0 The CTS input is assumed to be asynchronous with the data. When it is internally synchronized 

by the FCC, data is sent after a delay of no more than two serial clocks.

1 The CTS input is assumed to be synchronous with the data, giving faster operation. In this mode, 

CTS must transition while the transmit clock is in the low state. As soon as CTS is low, data 
transmission begins. This mode is useful when connecting PowerQUICC II in transparent mode 
because it allows the RTS signal of one PowerQUICC II to be connected directly to the CTS 
signal of another PowerQUICC II.

9--15

—

Reserved, should be 0. 

16–17

SYNL

Sync length (transparent mode only). Determines the operation of an FCC receiver configured for 
totally transparent operation only. See 

Section 37.3.1, “In-Line Synchronization Pattern

.”

00 The sync pattern in the FDSR is not used. An external sync signal is used instead (CD signal 

asserted: high to low transition).

01 Automatic sync (assumes always synchronized, ignores CD signal).
10 8-bit sync. The receiver synchronizes on an 8-bit sync pattern stored in the FDSR. Negation of 

CD causes CD lost error.

11 16-bit sync. The receiver synchronizes on a 16-bit sync pattern stored in the FDSR. Negation of 

CD causes CD lost error.

Note:

If SYNL = 1x, CDP should be cleared (not in CD pulse mode).

18

RTSM

RTS mode
0 Send idles between frames as defined by the protocol. RTS is negated between frames (default).
1 Send flags/syncs between frames according to the protocol. RTS is asserted whenever the FCC 

is enabled.

19–20

RENC

Receiver decoding method. The user should set RENC = TENC in most applications.
00 NRZ
01 NRZI (one bit mode HDLC or transparent only)
1x Reserved

21

REVD

Reverse data (valid for a totally transparent channel only)
0 Normal operation
1 The totally transparent channels on this FCC (either the receiver, transmitter, or both, as defined 

by TTX and TRX) reverse bit order, transmitting the MSB of each octet first.

22–23

TENC

Transmitter encoding method. The user should set TENC = RENC in most applications.
00 NRZ
01 NRZI (one bit mode HDLC or transparent only)
1x Reserved

24-25

TCRC

Transparent CRC (totally transparent channel only). Selects the type of frame checking provided on 
the transparent channels of the FCC (either the receiver, transmitter, or both, as defined by TTX and 
TRX). This configuration selects a frame check type; the decision to send the frame check is made 
in the TxBD. Thus, it is not required to send a frame check in transparent mode. If a frame check is 
not used, the user can ignore any frame check errors generated on the receiver.
00 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1)
01 Reserved
10 32-bit CCITT CRC (Ethernet and HDLC) (X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + 

X8 + X7 + X5 + X4 + X2 + X1 +1)

11 Reserved

Table 29-2. GFMR Register Field Descriptions (continued)

Bits

Name Description

Summary of Contents for MPC8250

Page 1: ...MPC8260 PowerQUICC II Family Reference Manual Supports MPC8250 MPC8255 MPC8260 MPC8264 MPC8265 MPC8266 MPC8260RM Rev 2 12 2005...

Page 2: ...for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a sit...

Page 3: ...Module Overview 14 Serial Interface with Time Slot Assigner 15 CPM Multiplexing 16 Baud Rate Generators BRGs 17 Timers 18 SDMA Channels and IDMA Emulation 19 Serial Communications Controllers SCCs 20...

Page 4: ...sor Module Overview 15 Serial Interface with Time Slot Assigner 16 CPM Multiplexing 17 Baud Rate Generators BRGs 18 Timers 19 SDMA Channels and IDMA Emulation 20 Serial Communications Controllers SCCs...

Page 5: ...Controller 36 FCC Transparent Controller 37 Serial Peripheral Interface SPI 38 I2 C Controller 39 Parallel I O Ports 40 Register Quick Reference Guide A Reference Manual Rev 1 Errata B Glossary of Te...

Page 6: ...DLC Controller 37 FCC Transparent Controller 38 Serial Peripheral Interface SPI 39 I2 C Controller 40 Parallel I O Ports A Register Quick Reference Guide B Reference Manual Rev 1 Errata GLO Glossary o...

Page 7: ...Processor Module CPM 1 9 1 3 Software Compatibility Issues 1 9 1 3 1 Signals 1 10 1 4 Differences between MPC860 and PowerQUICC II 1 12 1 5 Serial Protocol Table 1 12 1 6 PowerQUICC II Configurations...

Page 8: ...2 3 Programming Model 2 8 2 3 1 Register Set 2 8 2 3 1 1 PowerPC Register Set 2 9 2 3 1 2 PowerQUICC II Specific Registers 2 11 2 3 1 2 1 Hardware Implementation Dependent Register 0 HID0 2 11 2 3 1 2...

Page 9: ...r PIT 4 5 4 1 5 Software Watchdog Timer 4 6 4 2 Interrupt Controller 4 7 4 2 1 Interrupt Configuration 4 8 4 2 1 1 Machine Check Interrupt 4 9 4 2 1 2 INT Interrupt 4 9 4 2 2 Interrupt Source Prioriti...

Page 10: ...ol Register 2 TESCR2 4 40 4 3 2 12 Local Bus Transfer Error Status and Control Register 1 L_TESCR1 4 42 4 3 2 13 Local Bus Transfer Error Status and Control Register 2 L_TESCR2 4 43 4 3 2 14 Time Coun...

Page 11: ...s Bus Request BR Input 7 3 7 2 1 2 Bus Grant BG 7 4 7 2 1 2 1 Bus Grant BG Input 7 4 7 2 1 2 2 Bus Grant BG Output 7 4 7 2 1 3 Address Bus Busy ABB 7 5 7 2 1 3 1 Address Bus Busy ABB Output 7 5 7 2 1...

Page 12: ...2 1 Data Bus Busy DBB Output 7 12 7 2 6 2 2 Data Bus Busy DBB Input 7 12 7 2 7 Data Transfer Signals 7 12 7 2 7 1 Data Bus D 0 63 7 12 7 2 7 1 1 Data Bus D 0 63 Output 7 13 7 2 7 1 2 Data Bus D 0 63 I...

Page 13: ...16 8 4 3 7 60x Compatible Bus Mode Size Calculation 8 18 8 4 3 8 Extended Transfer Mode 8 19 8 4 4 Address Transfer Termination 8 22 8 4 4 1 Address Retried with ARTRY 8 22 8 4 4 2 Address Tenure Tim...

Page 14: ...ansactions 9 14 9 9 1 4 3 Data Streaming 9 14 9 9 1 4 4 Host Mode Configuration Access 9 15 9 9 1 4 5 Agent Mode Configuration Access 9 16 9 9 1 4 6 Special Cycle Command 9 16 9 9 1 4 7 Interrupt Ackn...

Page 15: ...9 11 2 3 PCI Bus Command Register 9 47 9 11 2 4 PCI Bus Status Register 9 48 9 11 2 5 Revision ID Register 9 49 9 11 2 6 PCI Bus Programming Interface Register 9 50 9 11 2 7 Subclass Code Register 9 5...

Page 16: ...und Post_FIFO Tail Pointer Register IPTPR 9 72 9 12 3 3 Outbound FIFOs 9 74 9 12 3 3 1 Outbound Free_FIFO Head Pointer Register OFHPR and Outbound Free_FIFO Tail Pointer Register OFTPR 9 74 9 12 3 3 2...

Page 17: ...1 1 2 Parity Error PERR 9 98 9 14 1 1 3 Error Reporting 9 98 9 14 1 2 Illegal Register Access Error 9 98 9 14 1 3 PCI Interface 9 98 9 14 1 3 1 Address Parity Error 9 99 9 14 1 3 2 Data Parity Error...

Page 18: ...pelining 11 9 11 2 10 External Memory Controller Support 11 10 11 2 11 External Address Latch Enable Signal ALE 11 10 11 2 12 ECC Parity Byte Select PBSE 11 10 11 2 13 Partial Data Valid Indication PS...

Page 19: ...al Address and Command Buffers BUFCMD 11 42 11 4 7 SDRAM Interface Timing 11 43 11 4 8 SDRAM Read Write Transactions 11 46 11 4 9 SDRAM Mode Set Command Timing 11 47 11 4 10 SDRAM Refresh 11 47 11 4 1...

Page 20: ...xx UPM and MPC82xx UPM 11 80 11 7 Memory System Interface Example Using UPM 11 81 11 7 0 1 EDO Interface Example 11 92 11 8 Handling Devices with Slow or Variable Access Times 11 101 11 8 1 Hierarchic...

Page 21: ...6 14 3 5 Peripheral Interface 14 7 14 3 6 Execution from RAM 14 8 14 3 7 RISC Controller Configuration Register RCCR 14 8 14 3 8 RISC Time Stamp Control Register RTSCR 14 11 14 3 9 RISC Time Stamp Reg...

Page 22: ...5 Static and Dynamic Routing 15 14 15 5 Serial Interface Registers 15 17 15 5 1 SI Global Mode Registers SIxGMR 15 17 15 5 2 SI Mode Registers SIxMR 15 17 15 5 3 SIx RAM Shadow Address Registers SIxRS...

Page 23: ...l Configuration Registers TGCR1 and TGCR2 18 3 18 2 3 Timer Mode Registers TMR1 TMR4 18 5 18 2 4 Timer Reference Registers TRR1 TRR4 18 6 18 2 5 Timer Capture Registers TCR1 TCR4 18 7 18 2 6 Timer Cou...

Page 24: ...6 19 8 1 Auto Buffer and Buffer Chaining 19 16 19 8 2 IDMAx Parameter RAM 19 17 19 8 2 1 DMA Channel Mode DCM 19 19 19 8 2 2 Data Transfer Types as Programmed in DCM 19 21 19 8 2 3 Programming DTS and...

Page 25: ...r 20 24 20 3 7 2 Reset Sequence for an SCC Transmitter 20 25 20 3 7 3 General Reconfiguration Sequence for an SCC Receiver 20 25 20 3 7 4 Reset Sequence for an SCC Receiver 20 25 20 3 7 5 Switching Pr...

Page 26: ...C HDLC Receive Buffer Descriptor RxBD 22 8 22 10 SCC HDLC Transmit Buffer Descriptor TxBD 22 11 22 11 HDLC Event Register SCCE HDLC Mask Register SCCM 22 12 22 12 SCC HDLC Status Register SCCS 22 14 2...

Page 27: ...Transparent Channel Frame Reception Process 24 2 24 4 Achieving Synchronization in Transparent Mode 24 3 24 4 1 Synchronization in NMSI Mode 24 3 24 4 1 1 In Line Synchronization Pattern 24 3 24 4 1...

Page 28: ...Hash Table Algorithm 25 12 25 12 Interpacket Gap Time 25 12 25 13 Handling Collisions 25 12 25 14 Internal and External Loopback 25 13 25 15 Full Duplex Ethernet Support 25 13 25 16 Handling Errors in...

Page 29: ...RT Channel Transmission Process 27 11 27 3 3 SMC UART Channel Reception Process 27 11 27 3 4 Programming the SMC UART Controller 27 11 27 3 5 SMC UART Transmit and Receive Commands 27 12 27 3 6 Sendin...

Page 30: ...CC Data Structure Organization 28 2 28 2 Global MCC Parameters 28 4 28 3 Channel Specific Parameters 28 5 28 3 1 Channel Specific HDLC Parameters 28 5 28 3 1 1 Internal Transmitter State TSTATE HDLC M...

Page 31: ...4 Superchannelling Programming Examples 28 30 28 6 MCC Configuration Registers MCCFx 28 33 28 7 MCC Commands 28 34 28 8 MCC Exceptions 28 35 28 8 1 MCC Event Register MCCE Mask Register MCCM 28 37 28...

Page 32: ...29 15 29 9 FCC Initialization 29 15 29 10 FCC Interrupt Handling 29 16 29 10 1 FCC Transmit Errors 29 16 29 10 1 1 Re Initialization Procedure 29 16 29 10 1 2 Recovery Sequence 29 17 29 10 1 3 Adjusti...

Page 33: ...nel 30 11 30 3 5 ATM Traffic Type 30 11 30 3 5 1 Peak Cell Rate Traffic Type 30 11 30 3 5 2 Determining the PCR Traffic Type Parameters 30 11 30 3 5 3 Peak and Sustain Traffic Type VBR 30 12 30 3 5 3...

Page 34: ...4 Clock Synchronization SRTS and Adaptive FIFOs 30 35 30 9 5 Mapping TDM Time Slots to VCs 30 35 30 9 6 CAS Support 30 35 30 9 7 Trunk Condition 30 36 30 9 8 ATM to ATM Data Forwarding 30 36 30 10 ATM...

Page 35: ...ee Buffer Pool Parameter Tables 30 70 30 10 5 3 ATM Controller Buffers 30 71 30 10 5 4 AAL5 RxBD 30 71 30 10 5 5 AAL1 RxBD 30 73 30 10 5 6 AAL0 RxBD 30 74 30 10 5 7 AAL1 CES RxBD 30 75 30 10 5 8 AAL2...

Page 36: ...n Service 31 1 Features 31 1 31 2 AAL1 CES Transmitter Overview 31 3 31 2 1 Data Path 31 3 31 2 2 Signaling Path 31 3 31 3 AAL1 CES Receiver Overview 31 4 31 4 Interworking Functions 31 6 31 4 1 Autom...

Page 37: ...BDs 31 40 31 13 AAL1 CES Exceptions 31 41 31 13 1 AAL1 CES Interrupt Queue Entry 31 41 31 14 AAL1 Sequence Number SN Protection Table 31 42 31 15 Internal AAL1 CES Statistics Tables 31 43 31 16 Extern...

Page 38: ...7 AAL2 Exceptions 32 38 Chapter 33 Inverse Multiplexing for ATM IMA 33 1 Features 33 1 33 1 1 References 33 3 33 1 2 IMA Versions Supported 33 3 33 1 3 PowerQUICC II Versions Supported 33 3 33 1 4 PHY...

Page 39: ...NTL 33 29 33 4 4 IMA Group Tables 33 29 33 4 4 1 IMA Group Transmit Table Entry 33 30 33 4 4 1 1 IMA Group Transmit Control IGTCNTL 33 31 33 4 4 1 2 IMA Group Transmit State IGTSTATE 33 31 33 4 4 1 3...

Page 40: ...UBR 33 57 33 4 9 2 Programming for ABR 33 57 33 4 10 Changing IMA Version 33 58 33 5 IMA Software Interface and Requirements 33 58 33 5 1 Software Model 33 58 33 5 2 Initialization Procedure 33 59 33...

Page 41: ...ponder FE 33 72 33 5 4 12 IDCR Operation 33 73 33 5 4 12 1 IDCR Start up 33 73 33 5 4 12 2 Activating a Group in IDCR Mode 33 74 33 5 4 13 End to End Channel Signalling Procedure 33 74 33 5 4 13 1 Tra...

Page 42: ...34 13 34 4 5 1 Receive 34 13 34 4 5 2 Transmit 34 13 34 5 Implementation Example 34 15 34 5 1 Operating the TC Layer at Higher Frequencies 34 16 34 5 2 Programming a T1 Application 34 16 34 5 3 Step...

Page 43: ...cessing 36 3 36 4 HDLC Parameter RAM 36 3 36 5 Programming Model 36 5 36 5 1 HDLC Command Set 36 5 36 5 2 HDLC Error Handling 36 6 36 6 HDLC Mode Register FPSMR 36 7 36 7 HDLC Receive Buffer Descripto...

Page 44: ...ransmit BD TxBD 38 15 38 8 SPI Master Programming Example 38 16 38 9 SPI Slave Programming Example 38 17 38 10 Handling Interrupts in the SPI 38 18 Chapter 39 I2 C Controller 39 1 Features 39 2 39 2 I...

Page 45: ...40 2 4 Port Pin Assignment Register PPAR 40 4 40 2 5 Port Special Options Registers A D PSORA PSORD 40 4 40 3 Port Block Diagram 40 5 40 4 Port Pins Functions 40 6 40 4 1 General Purpose I O Pins 40...

Page 46: ...MPC8260 PowerQUICC II Family Reference Manual Rev 2 xliv Freescale Semiconductor Contents Paragraph Number Title Page Number...

Page 47: ...Integrated Processor Core Block Diagram 2 2 2 2 PowerQUICC II Programming Model Registers 2 10 2 3 Hardware Implementation Register 0 HID0 2 11 2 4 Hardware Implementation Dependent Register 1 HID1 2...

Page 48: ...35 Time Counter Status and Control Register TMCNTSC 4 44 4 36 Time Counter Register TCMCNT 4 45 4 37 Time Counter Alarm Register TMCNTAL 4 45 4 38 Periodic Interrupt Status and Control Register PISCR...

Page 49: ...art for Embedded Utilities DMA Message Unit Mastered Transactions 9 23 9 14 Address Map Example 9 24 9 15 Inbound PCI Memory Address Translation 9 25 9 16 Outbound PCI Memory Address Translation 9 26...

Page 50: ...r 9 58 9 55 PCI Bus Arbiter Configuration Register 9 59 9 56 Hot Swap Register Block 9 60 9 57 Hot Swap Control Status Register 9 61 9 58 Data Structure for Register Initialization 9 64 9 59 PCI Confi...

Page 51: ...10 4 10 4 PLL Filtering Circuit 10 7 10 5 System Clock Control Register SCCR 10 8 10 6 System Clock Mode Register SCMR 10 9 10 7 Relationships of SCMR Parameters 10 10 11 1 Dual Bus Architecture 11 2...

Page 52: ...54 11 42 GPCM Peripheral Device Basic Timing ACS 1x and TRLX 0 11 54 11 43 GPCM Memory Device Interface 11 55 11 44 GPCM Memory Device Basic Timing ACS 00 CSNT 1 TRLX 0 11 55 11 45 GPCM Memory Device...

Page 53: ...Write Access to EDO DRAM Using REDO to Insert Three Wait States 11 96 11 80 Burst Read Access to EDO DRAM 11 97 11 81 Burst Write Access to EDO DRAM 11 98 11 82 Refresh Cycle CBR to EDO DRAM 11 99 11...

Page 54: ...c to Data xFSD 00 15 20 15 14 Falling Edge FE Effect When CE 1 and xFSD 01 15 21 15 15 Falling Edge FE Effect When CE 0 and xFSD 01 15 21 15 16 Falling Edge FE Effect When CE 1 and xFSD 00 15 22 15 17...

Page 55: ...7 Timing Requirement for DREQ Negation when IMDA Read from a Peripheral 19 15 19 8 IDMAx Channel s BD Table 19 17 19 9 DCM Parameters 19 19 19 10 IDMA Event Mask Registers IDSR IDMR 19 24 19 11 IDMA B...

Page 56: ...DLC Bus Multimaster Configuration 22 17 22 11 Typical HDLC Bus Single Master Configuration 22 18 22 12 Detecting an HDLC Bus Collision 22 19 22 13 Nonsymmetrical Tx Clock Duty Cycle for Increased Perf...

Page 57: ...SMC UART Event Register SMCE Mask Register SMCM 27 18 27 10 SMC UART Interrupts Example 27 19 27 11 Synchronization with SMSYNx 27 23 27 12 Synchronization with the TSA 27 24 27 13 SMC Transparent Rx...

Page 58: ...29 13 29 8 Output Delay from RTS Asserted 29 18 29 9 Output Delay from CTS Asserted 29 18 29 10 CTS Lost 29 19 29 11 Using CD to Control Reception 29 20 30 1 APC Scheduling Table Mechanism 30 9 30 2 V...

Page 59: ...ce Monitoring Table 30 62 30 38 ATM Pace Control Data Structure 30 64 30 39 The APC Scheduling Table Structure 30 65 30 40 Control Slot 30 66 30 41 Transmit Buffers and BD Table Example 30 67 30 42 Re...

Page 60: ...ve Slip Control 31 16 31 15 CES Adaptive Threshold Table 31 17 31 16 Pre Underrun Sequence 31 18 31 17 Pre Overrun Sequence 31 19 31 18 Recoverable Sync Fail sequence options 31 20 31 19 3 Step SN Alg...

Page 61: ...33 1 Basic Concept of IMA 33 5 33 2 Illustration of IMA Frames 33 6 33 3 IMA Microcode Overview 33 6 33 4 IMA Frame and ICP Cell Formats 33 10 33 5 IMA Transmit Task Interaction 33 12 33 6 Transmit Q...

Page 62: ...vent Register TCERx 34 10 34 8 TC Layer General Event Register TCGER 34 11 34 9 TC Layer General Status Register TCGSR 34 12 34 10 TC Operation in FCC External Rate Mode 34 14 34 11 TC Operation in FC...

Page 63: ...38 14 38 12 SPI TxBD 38 15 39 1 I2 C Controller Block Diagram 39 1 39 2 I2 C Master Slave General Configuration 39 2 39 3 I2 C Transfer Timing 39 3 39 4 I2 C Master Write Timing 39 3 39 5 I2 C Master...

Page 64: ...MPC8260 PowerQUICC II Family Reference Manual Rev 2 lxii Freescale Semiconductor Figures Figure Number Title Page Number...

Page 65: ...owerQUICC II s G2 Core and the MPC603e User s Manual 2 28 3 1 Internal Memory Map 3 1 4 1 System Configuration and Protection Functions 4 2 4 2 Interrupt Source Priority Levels 4 10 4 3 Encoding the I...

Page 66: ...12 8 4 Transfer Size Signal Encoding 8 13 8 5 Burst Ordering 8 14 8 6 Aligned Data Transfers 8 14 8 7 Unaligned Data Transfer Example 4 Byte Example 8 15 8 8 Data Bus Read Cycle Requirements and Writ...

Page 67: ...tions 9 54 9 33 GPLABARx Field Descriptions 9 55 9 34 Subsystem Vendor ID Register Description 9 56 9 35 Subsystem Device ID Description Register 9 56 9 36 PCI Bus Capabilities Pointer Register Descri...

Page 68: ...ins 10 6 10 2 SCCR Field Descriptions 10 8 10 3 SCMR Field Descriptions 10 10 10 4 60x Bus to Core Frequency 10 11 11 1 Number of PSDVAL Assertions Needed for TA Assertion 11 11 11 2 BADDR Connections...

Page 69: ...es Start Addresses 11 65 11 36 RAM Word Bit Settings 11 71 11 37 MxMR Loop Field Usage 11 76 11 38 UPM Address Multiplexing 11 77 11 39 60x Address Bus Partition 11 80 11 40 DRAM Device Address Port d...

Page 70: ...Typical Baud Rates for Asynchronous Communication 17 5 18 1 TGCR1 Field Descriptions 18 4 18 2 TGCR2 Field Descriptions 18 5 18 3 TMR1 TMR4 Field Descriptions 18 6 18 4 TER Field Descriptions 18 8 19...

Page 71: ...and Control Field Descriptions 21 17 21 11 SCC UART TxBD Status and Control Field Descriptions 21 18 21 12 SCCE SCCM Field Descriptions for UART Mode 21 21 21 13 UART SCCS Field Descriptions 21 22 21...

Page 72: ...ernet Parameter RAM Memory Map 25 7 25 2 Transmit Commands 25 10 25 3 Receive Commands 25 10 25 4 Transmission Errors 25 13 25 5 Reception Errors 25 14 25 6 PSMR Field Descriptions 25 15 25 7 SCC Ethe...

Page 73: ...iption 28 22 28 12 Parameter Values for SUERM in Japanese SS7 28 24 28 13 SS7 Configuration Register Fields Description 28 24 28 14 Channel Extra Parameters 28 28 28 15 MCCF Field Descriptions 28 33 2...

Page 74: ...Protocol Specific TCT Field Descriptions 30 56 30 24 AAL0 Specific TCT Field Descriptions 30 57 30 25 VBR Specific TCTE Field Descriptions 30 58 30 26 UBR Protocol Specific TCTE Field Descriptions 30...

Page 75: ...15 AAL1 CES External Statistics Table 31 44 32 1 AAL2 Protocol Specific Transmit Connection Table TCT Field Descriptions 32 11 32 2 CPS TxQD Field Descriptions 32 14 32 3 CPS TxBD Field Descriptions...

Page 76: ...s IDCR Master Clock 33 53 33 25 IDCR IMA Root Parameters 33 54 33 26 IDCR Table Entry 33 54 33 27 IDSR IDMR Field Descriptions 33 55 33 28 Examples of APC Programming for IMA 33 56 33 29 COMM_INFO Fie...

Page 77: ...mory Map 38 11 38 6 RFCR TFCR Field Descriptions 38 12 38 7 SPI Commands 38 12 38 8 SPI RxBD Status and Control Field Descriptions 38 14 38 9 SPI TxBD Status and Control Field Descriptions 38 15 39 1...

Page 78: ...anual Rev 2 lxxvi Freescale Semiconductor Tables Table Number Title Page Number A 2 User Level PowerPC SPRs A 1 A 3 Supervisor Level PowerPC Registers A 2 A 4 Supervisor Level PowerPC SPRs A 2 A 5 MPC...

Page 79: ...understanding the PowerQUICC II core it does not contain a complete description of the architecture Where additional information might help the reader references are made to Programming Environments M...

Page 80: ...4 1 Hard Reset Configuration Word Note The References list includes the chapters that contain the greatest additions but it does not list every chapter that has additions Chapter 1 Overview Chapter 3...

Page 81: ...ughly follows the structure of this book summarizing the relevant features and providing references for the reader who needs additional information Chapter 2 G2 Core provides an overview of the PowerQ...

Page 82: ...Test Access Port and Boundary Scan Architecture Part IV Communications Processor Module describes the configuration clocking and operation of the various communications protocols supported by the Powe...

Page 83: ...Chapter 30 ATM Controller and AAL0 AAL1 and AAL5 describes the PowerQUICC II ATM controller which provides the ATM and AAL layers of the ATM protocol The ATM controller performs segmentation and reas...

Page 84: ...general information about the PowerPC architecture MPC82xx Documentation Supporting documentation for the PowerQUICC II can be accessed through the world wide web at www freescale com This documentati...

Page 85: ...tax used to identify a source GPR rD Instruction syntax used to identify a destination GPR REG FIELD Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text Specific...

Page 86: ...a address register DEC Decrementer register DMA Direct memory access DPLL Digital phase locked loop DRAM Dynamic random access memory DSISR Register used for determining the source of a DSI exception...

Page 87: ...d invalid cache coherency protocol MMU Memory management unit MSB Most significant byte msb Most significant bit MSR Machine state register NaN Not a number NIA Next instruction address NMSI Nonmultip...

Page 88: ...hine status save restore register 0 SRR1 Machine status save restore register 1 TAP Test access port TB Time base register TDM Time division multiplexed TLB Translation lookaside buffer TSA Time slot...

Page 89: ...e interrupt DSI DSI exception Extended mnemonics Simplified mnemonics Instruction storage interrupt ISI ISI exception Interrupt Exception Privileged mode or privileged state Supervisor level privilege...

Page 90: ...MPC8260 PowerQUICC II Family Reference Manual Rev 2 lxxxviii Freescale Semiconductor...

Page 91: ...rs are mapped in memory It includes cross references that indicate where the registers are described in detail Conventions Part I uses the following notational conventions mnemonics Instruction mnemon...

Page 92: ...DAR Data address register DEC Decrementer register DMA Direct memory access DPLL Digital phase locked loop DRAM Dynamic random access memory DTLB Data translation lookaside buffer EA Effective addres...

Page 93: ...Serial communications controller SDLC Synchronous data link control SDMA Serial DMA SI Serial interface SIU System interface unit SMC Serial management controller SPI Serial peripheral interface SPR...

Page 94: ...MPC8260 PowerQUICC II Family Reference Manual Rev 2 I 4 Freescale Semiconductor...

Page 95: ...PowerQUICC MPC860 with the addition of three high performance communication channels that support new emerging protocols for example 155 Mbps ATM and Fast Ethernet The PowerQUICC II has dedicated har...

Page 96: ...hip memory controller Supports data parity or ECC and address parity 32 bit data and 18 bit address local bus Single master bus supports external slaves Eight beat burst transfers 32 16 and 8 bit port...

Page 97: ...e following protocols 10 100 Mbit Ethernet IEEE 802 3 CDMA CS interface through media independent interface MII ATM not on MPC8250 full duplex SAR at 155 Mbps UTOPIA interface AAL5 AAL1 AAL0 protocols...

Page 98: ...nd FCC2 to support inverse multiplexing for ATM capabilities IMA MPC8264 and MPC8266 only Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCC SCC and SMC serial...

Page 99: ...ror and corrected cells Idle unassigned cells filtered Idle unassigned cells transmitted Transmitted ATM cells Received ATM cells Maskable interrupt is sent to the host when a counter expires Overrun...

Page 100: ...s signals so there is no need for additional pins 1 2 Architecture Overview The PowerQUICC II has two external buses to accommodate bandwidth requirements from the high speed system core and the very...

Page 101: ...ytes of data cache It has a 64 bit split transaction external data bus which is connected directly to the external PowerQUICC II pins 16 Kbytes G2 Core I Cache I MMU 16 Kbytes D Cache D MMU Communicat...

Page 102: ...y high speed communication controllers Without requiring extensive manipulation by the core the bus can be used to store connection tables for ATM or buffer descriptors BDs for the communication chann...

Page 103: ...interface there are two UTOPIA interfaces on the PowerQUICC II IEEE 802 3 and Fast Ethernet protocols HDLC up to E3 rates 45 Mbps and totally transparent operation Each FCC can be configured to trans...

Page 104: ...by function Note that many of these signals are multiplexed and this figure does not indicate how these signals are multiplexed NOTE A bar over a signal name indicates that the signal is active low fo...

Page 105: ...I_C BE 0 3 1 LCL_DP 0 3 4 1 NC DP0 RSRV EXT_BR2 1 IRQ1 DP1 EXT_BG2 1 IRQ2 DP2 TLBISYNC EXT_DBG2 PCI_CFG 3 0 1 LBS 0 3 LSDDQM 0 3 LWE 0 3 4 M E M C 1 IRQ3 DP3 CKSTP_OUT EXT_BR3 PCI_MODCK_H01 LGPL0 LSDA...

Page 106: ...he same functionality True little endian mode PCMCIA interface Infrared IR port QMC protocol in SCC 256 HDLC channels are supported by the MCCs Multiply and accumulate MAC block in the CPM Centronics...

Page 107: ...serial channels Serial rate and protocol versus CPM clock frequency for CP protocol handling Serial rate and protocol versus bus bandwidth Serial rate and protocol versus system core clock for adequat...

Page 108: ...tions describe the following examples of communication systems Section 1 7 1 1 Remote Access Server Section 1 7 1 2 Regional Office Router Section 1 7 1 3 LAN to WAN Bridge Router Section 1 7 1 4 Cell...

Page 109: ...external memory on the local bus for example 128 active internal connections require 8 Kbytes of dual port RAM The need for local bus depends on the total throughput of the system The PowerQUICC II su...

Page 110: ...TDM port supports 32 128 channels If 128 channels are needed each TDM port can be configured to support 32 channels This example has two MII ports for 10 100 BaseT LAN connections In all the examples...

Page 111: ...tion Examples Figure 1 6 Cellular Base Station Configuration PowerQUICC II 60x Bus SDRAM DRAM SRAM Local Bus SDRAM DRAM SRAM ATM Connection Tables optional MII Transceiver 10 100BaseT 155 Mbps PHY ATM...

Page 112: ...efer to note at the beginning of Section 1 7 Application Examples Figure 1 7 Telecommunications Switch Controller Configuration The PowerQUICC II CPM supports a total aggregate throughput of 710 Mbps...

Page 113: ...nce System Microprocessor Section 1 7 2 4 PCI MPC8250 MPC8265 and MPC8266 only Section 1 7 2 5 PCI with 155 Mbps ATM MPC8265 and MPC8266 only Section 1 7 2 6 PowerQUICC II as PCI Agent MPC8250 MPC8265...

Page 114: ...nication Figure 1 10 shows a high performance communication configuration Figure 1 10 High Performance Communication PowerQUICC II 60x Bus SDRAM SRAM DRAM Flash Local Bus SDRAM SRAM DRAM ATM Connectio...

Page 115: ...ation with a high performance system microprocessor MPC750 Refer to note at the beginning of Section 1 7 Application Examples Figure 1 11 High Performance System Microprocessor Configuration In this s...

Page 116: ...us 1 7 2 5 PCI with 155 Mbps ATM Figure 1 13 shows the PCI with 155 Mbps ATM configuration MPC8265 and MPC8266 only Figure 1 13 PCI with 155 Mbps ATM Configuration This system supports PCI and impleme...

Page 117: ...iguration when the PowerQUICC II acts as the PCI agent refer to note at the beginning of Section 1 7 Application Examples Figure 1 14 PowerQUICC II as PCI Agent In this system the PowerQUICC II is a P...

Page 118: ...Overview MPC8260 PowerQUICC II Family Reference Manual Rev 2 1 24 Freescale Semiconductor...

Page 119: ...describes the details of the processor core provides a block diagram showing the major functional units and describes briefly how those units interact The signals associated with the processor core a...

Page 120: ...Point Unit FPR File FP Rename Registers 16 Kbyte D Cache Tags Sequential Fetcher CTR CR LR FPSCR System Register Unit Core Interface D MMU SRs DTLB DBAT Array Touch Load Buffer Copy Back Buffer 64 Bi...

Page 121: ...he TLBs and caches use a least recently used LRU replacement algorithm The processor core also supports block address translation through the use of two independent instruction and data block address...

Page 122: ...ressed LRU replacement algorithm Cache write back or write through operation programmable on a per page or per block basis Address translation facilities for 4 Kbyte page size variable block size and...

Page 123: ...sequential execution If any of these instructions are to be executed in the BPU they are decoded but not issued Instructions to be executed by the IU LSU and SRU are issued and allowed to complete up...

Page 124: ...etic logic unit ALU multiplier divider and XER register Most integer instructions are single cycle instructions Thirty two general purpose registers are provided to support integer operations Stalls d...

Page 125: ...ns issued have completed Results from completion serialized instructions executed by the SRU are not available or forwarded for subsequent instructions until the instruction completes 2 2 5 Completion...

Page 126: ...ruction fetch units provide the caches with the address of the data or instruction to be fetched In the case of a cache hit the cache returns two words to the requesting unit 2 3 Programming Model The...

Page 127: ...The general purpose registers GPRs and floating point registers FPRs are accessed through instruction operands Access to registers can be explicit that is through the use of specific instructions for...

Page 128: ...sters1 SPR 976 DMISS SPR 977 DCMP SPR 978 HASH1 SPR 979 HASH2 SPR 980 IMISS SPR 981 ICMP SPR 982 RPA Machine State Register MSR Processor Version Register SPR 287 PVR Configuration Registers Hardware...

Page 129: ...30 31 ICE DCE ILOCK DLOCK ICFI DCFI IFEM FBIOB ABE NOOPTI Figure 2 3 Hardware Implementation Register 0 HID0 Table 2 1 HID0 Field Descriptions Bits Name Description 0 EMCP Enable machine check input p...

Page 130: ...Not hard reset software use only Helps software distinguish a hard reset from a soft reset 0 A hard reset occurred if software had previously set this bit 1 A hard reset has not occurred If software...

Page 131: ...he cache are signaled as a miss during invalidate all operations Setting ICFI clears all the valid bits of the blocks and the PLRU bits to point to way L0 of each set Once the L1 flash invalidate bits...

Page 132: ...he Operation of the G2 Core Reference Manual for more information 0 4 5 31 PLLCFG Figure 2 4 Hardware Implementation Dependent Register 1 HID1 Table 2 2 HID1 Field Descriptions Bits Name Function 0 4...

Page 133: ...h immediate index EA rA 0 rB register indirect with index These simple addressing modes allow efficient address generation for memory accesses Calculation of the effective address for aligned transfer...

Page 134: ...ore with byte reverse Integer load and store string multiple Floating point load and store Flow control instructions These include branching instructions condition register logical instructions trap i...

Page 135: ...can be interrupted directly by the execution of an instruction or by an asynchronous event Either kind of exception may cause one of several components of the system software to be invoked 2 3 2 3 Pow...

Page 136: ...aded from an 8 word boundary that is bits A27 A31 of the effective addresses are zero thus a cache block never crosses a page boundary Misaligned accesses across a page boundary can incur a performanc...

Page 137: ...tivity for example when a snooped read access hits a modified line in the cache Setting HID0 ABE causes execution of the dcbf dcbi and dcbst instructions to be broadcast onto the 60x bus The value of...

Page 138: ...erwritten Cache entries can be locked for either an entire cache or for individual ways within the cache Entire data cache locking is enabled by setting HID0 DLOCK and entire instruction cache locking...

Page 139: ...re recognized when they occur but are not handled until the instruction currently in the completion stage successfully completes execution or generates an exception and the completed store queue is em...

Page 140: ...e or imprecise and either synchronous or asynchronous Asynchronous exceptions some of which are maskable are caused by events external to the processor s execution Synchronous exceptions which are all...

Page 141: ...is to a direct store segment indicated by SRR1 3 set The fetch access violates memory protection indicated by SRR1 4 set If the key bits Ks and Kp in the segment register and the PP bits in the PTE ar...

Page 142: ...he floating point available bit is cleared MSR FP 0 Decrementer 00900 The decrementer exception occurs when the most significant bit of the decrementer DEC register transitions from 0 to 1 Must also b...

Page 143: ...by an executing program The PowerPC architecture supports the following three translation methods Address translations disabled Translation is enabled by setting bits in the MSR MSR IR enables instruc...

Page 144: ...order bits of the effective address are translated by the appropriate MMU into physical address bits Simultaneously the lower order address bits that are untranslated and therefore considered both lo...

Page 145: ...line stage each execution unit that has an executable instruction executes the selected instruction perhaps over multiple cycles writes the instruction s result into the appropriate rename register an...

Page 146: ...lity to broadcast dcbf dcbi and dcbst onto the 60x bus Setting HID0 ABE enables the new broadcast feature new in the PID7v 603e The default is to not broadcast these operations Added ability to reflec...

Page 147: ...l Port RAM 0x00000 0x03FFF Dual port RAM DPRAM1 R W 16 Kbytes 14 5 14 17 0x04000 0x05FFF Dual port RAM microcode only DPRAM 1 R W 8 Kbytes 14 5 14 17 0x06000 0x07FFF Reserved 8 Kbytes 0x08000 0x08FFF...

Page 148: ...10050 60x bus DMA transfer error address PDTEA R 32 bits undefined 19 2 3 19 4 0x10054 60x bus DMA transfer error MSNUM PDTEM R 8 bits undefined 19 2 4 19 4 0x10055 Reserved 24 bits 0x10058 Local bus...

Page 149: ...undefined 11 3 2 11 15 0x10160 Reserved 8 bytes 0x10168 Memory address register MAR R W 32 bits undefined 11 3 7 11 29 0x1016C Reserved 32 bits 0x10170 Machine A mode register MAMR R W 32 bits 0x0004...

Page 150: ...er alarm register TMCNTAL R W 32 bits 0x0000_0000 4 3 2 16 4 45 0x10230 0x1023F Reserved 16 bytes 0x10240 Periodic interrupt status and control register PISCR R W 16 bits 0x0000 4 3 3 1 4 46 0x10244 P...

Page 151: ...2 R W 32 bits 0x0000_0002 9 12 3 4 7 9 83 0x104F0 Queue base address register QBAR 2 R W 32 bits 0x0000_0000 9 12 3 4 8 9 84 0x10500 DMA 0 mode register DMAMR0 2 R W 32 bits 0x0000_0000 9 13 1 6 1 9...

Page 152: ...x0000_0000 9 11 1 5 9 31 0x10818 PCI outbound translation address register 1 POTAR1 2 R W 32 bits 0x0000_0000 9 11 1 3 9 30 0x10820 PCI outbound base address register 1 POBAR1 2 R W 32 bits 0x0000_000...

Page 153: ...0 SIU interrupt priority register SIPRR R W 32 bits 0x0530_9770 4 3 1 2 4 18 0x10C14 CPM interrupt priority register high SCPRR_H R W 32 bits 0x0530_9770 4 3 1 3 4 19 0x10C18 CPM interrupt priority re...

Page 154: ...register PODRC R W 32 bits 0x0000_0000 40 2 1 40 1 0x10D50 Port C data register PDATC R W 32 bits 0x0000_0000 40 2 2 40 2 0x10D54 0x10D5F Reserved 12 bytes 0x10D60 Port D data direction register PDIRD...

Page 155: ...2 6 18 7 0x10DAE Timer 4 counter TCN4 R W 16 bits 0x0000 18 2 6 18 7 0x10DB0 Timer 1 event register TER1 R W 16 bits 0x0000 18 2 7 18 7 0x10DB2 Timer 2 event register TER2 R W 16 bits 0x0000 18 2 7 18...

Page 156: ...ic mode register FPSMR1 R W 32 bits 0x0000_0000 30 13 2 30 88 ATM 33 4 2 1 1 33 26 IMA 35 18 1 35 18 Ethernet 36 6 36 7 HDLC 0x11308 FCC1 transmit on demand register FTODR1 R W 16 bits 0x0000 29 5 29...

Page 157: ...ific mode register FPSMR2 R W 32 bits 0x0000_0000 30 13 2 30 88 ATM 33 4 2 1 1 33 26 IMA 35 18 1 35 18 Ethernet 36 6 36 7 HDLC 0x11328 FCC2 transmit on demand register FTODR2 R W 16 bits 0x0000 29 5 2...

Page 158: ...MR3 3 R W 32 bits 0x0000_0000 30 13 2 30 88 ATM 33 4 2 1 1 33 26 IMA 35 18 1 35 18 Ethernet 36 6 36 7 HDLC 0x11348 FCC3 transmit on demand register FTODR3 3 R W 16 bits 0x0000 29 5 29 8 0x1134A Reserv...

Page 159: ...SMR2 4 R W 16 bits 0x0000 34 4 1 2 34 9 0x11424 TC2 event register TCER2 4 R W 16 bits 0x0000 34 4 1 3 34 10 0x11426 TC2 received cells counter TC_RCC2 4 R W 16 bits 0x0000 34 4 1 4 34 11 0x11428 TC2...

Page 160: ...TC_ICC4 4 R W 16 bits 0x0000 34 4 3 5 34 12 0x11470 TC4 transmitted cells counter TC_TCC4 4 R W 16 bits 0x0000 34 4 3 2 34 12 0x11472 TC4 error cells counter TC_ECC4 4 R W 16 bits 0x0000 34 4 3 3 34...

Page 161: ...6 bits 0x0000 34 4 1 4 34 11 0x114C8 TC7 mask register TCMR7 4 R W 16 bits 0x0000 34 4 1 4 34 11 0x114CA TC7 filtered cells counter TC_FCC7 4 R W 16 bits 0x0000 34 4 3 6 34 13 0x114CC TC7 corrected ce...

Page 162: ...served 608 bytes I2 C 0x11860 I2C mode register I2MOD R W 8 bits 0x00 39 4 1 39 6 0x11861 Reserved 24 bits 0x11864 I2C address register I2ADD R W 8 bits 0x00 39 4 2 39 6 0x11865 Reserved 24 bits 0x118...

Page 163: ...RGC4 R W 32 bits 0x0000_0000 SCC1 0x11A00 SCC1 general mode register GSMR_L1 R W 32 bits 0x0000_0000 20 1 1 20 3 0x11A04 SCC1 general mode register GSMR_H1 R W 32 bits 0x0000_0000 0x11A08 SCC1 protoco...

Page 164: ...ode register PSMR2 R W 16 bits 0x0000 20 1 2 20 9 21 16 21 12 UART 22 8 22 7 HDLC 23 11 23 10 BISYNC 24 9 24 8 Transparent 25 17 25 14 Ethernet 0x11A2A Reserved 16 bits 0x11A2C SCC2 transmit on demand...

Page 165: ...egister PSMR3 R W 16 bits 0x0000 20 1 2 20 9 21 16 21 12 UART 22 8 22 7 HDLC 23 11 23 10 BISYNC 24 9 24 8 Transparent 25 17 25 14 Ethernet 0x11A4A Reserved 16 bits 0x11A4C SCC3 transmit on demand regi...

Page 166: ...21 12 UART 22 8 22 7 HDLC 23 11 23 10 BISYNC 24 9 24 8 Transparent 25 17 25 14 Ethernet 0x11A6A Reserved 16 bits 0x11A6C SCC4 transmit on demand register TODR4 R W 16 bits 0x0000 20 1 4 20 10 0x11A6E...

Page 167: ...27 3 11 27 18 UART 27 4 10 27 28 Transparent 27 5 9 27 34 GCI 0x11A97 Reserved 24 bits 0x11A9A SMC2 mask register SMCM2 R W 8 bits 0x00 0x11A9B 0x11A9F Reserved 5 bytes SPI 0x11AA0 SPI mode register S...

Page 168: ...I1 TDMC1 mode register SI1CMR R W 16 bits 0x0000 0x11B26 SI1 TDMD1 mode register SI1DMR R W 16 bits 0x0000 0x11B28 SI1 global mode register SI1GMR R W 8 bits 0x00 15 5 1 15 17 0x11B29 Reserved 8 bits...

Page 169: ...hadow address register SI2RSR R W 16 bits 0x0000 15 5 3 15 23 MCC2 Registers 0x11B50 MCC2 event register MCCE2 R W 16 bits 0x0000 28 8 1 28 37 0x11B52 Reserved 16 bits 0x11B54 MCC2 mask register MCCM2...

Page 170: ...137FF Reserved 2048 bytes 0x13800 0x13FFF Reserved 2048 bytes 1 25 m HiP4 devices only Reserved on 29 m HiP3 devices 2 MPC8250 MPC8265 and MPC8266 only Reserved on all other devices 3 Reserved on the...

Page 171: ...d start up Suggested Reading Supporting documentation for the PowerQUICC II can be accessed through the world wide web at www freescale com This documentation includes technical specifications referen...

Page 172: ...s SDR1 and DSISR are historical and the words for which an acronym stands may not be intuitively obvious Table II 1 Acronyms and Abbreviated Terms Term Meaning BIST Built in self test DMA Direct memor...

Page 173: ...Flexible high performance memory controller Level two cache controller interface PCI interface MPC8250 MPC8265 and MPC8266 only IEEE 1149 1 test access port TAP Figure 4 1 is a block diagram of the S...

Page 174: ...60x bus monitor Monitors the transfer acknowledge TA and address acknowledge AACK response time for all bus accesses initiated by internal or external masters TEA is asserted if the TA AACK response l...

Page 175: ...tinues until the whole data tenure is completed Following the data tenure the bus monitor will idle in case there is no pending transaction otherwise it will reload the time out value and resume count...

Page 176: ...pplication software The counter is reset to zero on PORESET reset or hard reset but is not effected by soft reset It is initialized by the software the user should set the timersclk frequency to 8 192...

Page 177: ...hen a new value is loaded into the PITC the PIT is updated the divider is reset and the counter begins counting Setting PS creates a pending interrupt that remains pending until PS is cleared If PS is...

Page 178: ...he state of SWE cannot be changed The software watchdog timer service sequence consists of the following two steps 1 Write 0x556C to the software service register SWSR 2 Write 0xAA39 to SWSR The servi...

Page 179: ...to SWTC the software watchdog timer is not updated until the servicing sequence is written to the SWSR If SYPCR SWE is loaded with 0 the modulus counter does not count 4 2 Interrupt Controller Key fea...

Page 180: ...roller and from external pins port C parallel I O pins Figure 4 8 PowerQUICC II Interrupt Structure MCP IRQ 0 7 INT OR G2 Core Port C 0 15 Timer1 Timer2 Timer3 Timer4 SCC3 SCC4 SMC1 SPI I2C SMC2 Softw...

Page 181: ...vector register SIVEC is updated with a 6 bit vector corresponding to the sub block with the highest current priority 4 2 1 1 Machine Check Interrupt There are several sources for a machine check inte...

Page 182: ...Interrupt Source Description Multiple Events 1 Highest 2 XSIU1 No TMCNT PIT PCI1 Yes 3 XSIU2 Grouped No TMCNT PIT PCI1 Yes 4 XSIU3 Grouped No TMCNT PIT PCI1 Yes 5 XSIU4 Grouped No TMCNT PIT PCI1 Yes 6...

Page 183: ...Parallel I O PC11 No 39 IDMA2 Yes 40 Timer 2 Yes 41 Parallel I O PC10 No 42 XSIU5 GSIU 1 No TMCNT PIT PCI1 Yes 43 YCC3 Spread Yes 44 RISC Timer Table Yes 45 I2C Yes 46 YCC4 Spread Yes 47 Parallel I O...

Page 184: ...XCC8 and YCC1 YCC8 Each SCC can be mapped to any YCC location and each FCC and MCC can be mapped to any XCC location The SCC FCC and MCC priorities are programmed in the CPM interrupt priority regist...

Page 185: ...ghest priority feature is not used select the interrupt request in XSIU1 to be the highest priority interrupt the standard interrupt priority order is used SICR HP can be updated dynamically to allow...

Page 186: ...to the core by reading SIVEC The interrupt controller passes an interrupt vector corresponding to the highest priority unmasked pending interrupt Table 4 3 lists encodings for the six low order bits...

Page 187: ...01_0001 18 PCI1 0b01_0010 19 IRQ1 0b01_0011 20 IRQ2 0b01_0100 21 IRQ3 0b01_0101 22 IRQ4 0b01_0110 23 IRQ5 0b01_0111 24 IRQ6 0b01_1000 25 IRQ7 0b01_1001 26 31 Reserved 0b01_1010 01_1111 32 FCC1 0b10_00...

Page 188: ...n interrupt request signal to be sent to the interrupt controller PC 0 15 lines can be programmed to assert an interrupt request upon any change Each port C line asserts a unique interrupt request to...

Page 189: ...s are described in Section 4 3 2 System Configuration and Protection Registers Periodic interrupt registers These include registers for configuring and providing status for periodic interrupts See Sec...

Page 190: ...be modified dynamically To retain the original priority program HP to the interrupt number assigned to XSIU1 8 13 Reserved should be cleared 14 GSIU Group SIU Selects the relative XSIU priority scheme...

Page 191: ...00 TMCNT asserts its request in the XSIU1 position 001 PIT asserts its request in the XSIU1 position 010 PCI asserts its request in the XSIU1 position MPC8250 MPC8265 and MPC8266 only Reserved on all...

Page 192: ...tion 001 FCC2 asserts its request in the XCC1 position 010 FCC3 asserts its request in the XCC1 position 1 011 XCC1 position not active 100 MCC1 asserts its request in the XCC1 position 2 101 MCC2 ass...

Page 193: ...asserts its request in the YCC1 position 011 SCC4 asserts its request in the YCC1 position 100 TC layer asserts its request in the YCC1 position MPC8264 and MPC8266 only Reserved on other devices 1XX...

Page 194: ...sponding SIMR bit When a masked interrupt occurs the corresponding SIPNR bit is set regardless of the SIMR bit although no interrupt request is passed to the core If an interrupt source requests inter...

Page 195: ...tor cannot be masked 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 Reset 0000_0000_0000_0000 R W R W Addr 0x0x10C1C 16 17 18 19 20 2...

Page 196: ...a branch table can be used in which each entry contains one instruction branch When read as a half word each entry can contain a full routine of up to 256 instructions The interrupt code is defined s...

Page 197: ...SIU external interrupt control register SIEXR shown in Figure 4 20 determines whether the corresponding port C line asserts an interrupt request upon either a high to low change or any change on the p...

Page 198: ...13 EDPC 14 EDPC 15 Reset 0000_0000_0000_0000 R W R W Addr 0x0x10C24 16 17 18 19 20 21 22 23 24 31 Field EDI0 EDI1 EDI2 EDI3 EDI4 EDI5 EDI6 EDI7 Reset 0000_0000_0000_0000 R W R W R Addr 0x10C26 Figure...

Page 199: ...ces APD indicates how many cycles the PowerQUICC II should wait for ARTRY but because it is assumed that ARTRY can be asserted by other masters only on cachable address spaces APD is considered only o...

Page 200: ...nes odd or even parity on the 60x bus 0 Odd parity 1 Even parity Writing the memory with EPAR 1 and reading the memory with EPAR 0 generates parity errors for testing 15 LEPAR Local bus even parity De...

Page 201: ...pace controlled by the memory controller 1 The memory controller asserts CS on the cycle following the assertion of TS by external master accessing an address space controlled by the memory controller...

Page 202: ...bitration 0 Internal arbitration is performed See Section 8 3 1 Arbitration Phase 1 External arbitration is assumed 4 7 PRKM Parking master 0000 CPM high request level refers to the IDMA which involve...

Page 203: ...riority Field 8 Priority Field 9 Priority Field 10 Priority Field 11 Reset 1000 1001 1010 1011 R W R W Addr 0x0x10030 16 19 20 23 24 27 28 31 Field Priority Field 12 Priority Field 13 Priority Field 1...

Page 204: ...high request level refers to the IDMA which involves peripherals and the following serial channels SCC SPI SMC and I2 C 0001 CPM middle request level refers to all other serial channels FCCs and MCCs...

Page 205: ...15 Reset 1100 1101 1110 1111 R W R W Addr 0x1003E Figure 4 27 LCL_ALRL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field BBD ESE PBSE CDIS DPPC L2CPC LBPC APPC CS10PC BCTLC Reset see note 00 see note 00 R...

Page 206: ...deactivates these lines Pin DPPC 00 01 10 11 DP 0 RSRV DP 0 RSRV EXT_BR2 DP 1 IRQ1 IRQ1 DP 1 IRQ1 EXT_BG2 DP 2 TLBISYNC IRQ2 IRQ2 DP 2 TLBISYNC EXT_DBG2 DP 3 IRQ3 IRQ3 DP 3 CKSTP_OU T EXT_BR3 DP 4 IRQ...

Page 207: ...WE control for external buffers BCTL1 is used as RE control for external buffers 11 Reserved 16 17 MMR Mask masters requests In some systems several bus masters are active during normal operation only...

Page 208: ...le 4 13 describes IMMR fields 18 LPBSE Local bus parity byte select enable 0 Parity byte select is disabled LGPL4 output of UPM is available for memory control 1 Parity byte select is enabled LGPL4 pi...

Page 209: ...location of internal space depends on the internal memory space of a specific implementation In the PowerQUICC II all 15 bits can be programmed See Chapter 3 Memory Map for details on the device s in...

Page 210: ...itor the granularity of this field is 8 bus clocks BMT 0xFF is translated to 0x7f8 clock cycles BMT is used both in the 60x and local bus monitors Note that the value 0 in invalid an error is generate...

Page 211: ...ndicate which of PowerQUICC II s internal slaves caused the error TESCR2 PCI0 PCI1 are only on the MPC8250 the MPC8265 and the MPC8266 2 PAR 60x bus parity error Indicates that an MCP was caused due t...

Page 212: ...n and forward Data error Set when a core machine check is asserted due to ECC or parity errors 21 29 m HiP3 Rev A devices Reserved should be cleared IRQ0 29 m HiP3 Rev B 3 silicon and forward External...

Page 213: ...erQUICC II s dual port RAM 3 Reserved should be cleared 4 Reserved should be cleared PCI0 MPC8250 MPC8265 and MPC8266 only PCI memory space 0 error An error occurred in a transaction to the PCI memory...

Page 214: ...d due to the local bus monitor time out 1 Reserved should be cleared 2 PAR Parity error Indicates that MCP was asserted due to parity error on the local bus L_TESCR2 PB indicates the byte lane that ca...

Page 215: ...12 15 Field PB Reset 0000_0000_0000_0000 R W R W Addr 0x0x1004C 16 27 28 31 Field BNK Reset 0000_0000_0000_0000 R W R W Addr 0x1004E Note all bits are status bits and are cleared by writing 1s Figure...

Page 216: ...nd Control Register TMCNTSC Table 4 19 TMCNTSC Field Descriptions Bits Name Description 0 7 Reserved should be cleared 8 SEC Once per second interrupt This status bit is set every second and should be...

Page 217: ...Field TMCNT Reset 0000_0000_0000_0000 R W R W Addr 0x0x10224 16 31 Field TMCNT Reset 0000_0000_0000_0000 R W R W Addr 0x10226 Figure 4 36 Time Counter Register TCMCNT 0 15 Field ALARM Reset 0000_0000...

Page 218: ...able 4 21 PISCR Field Descriptions Bits Name Description 0 7 Reserved should be cleared 8 PS Periodic interrupt status Asserted if the PIT issues an interrupt The PIT issues an interrupt after the mod...

Page 219: ...set 0000_0000_0000_0000 R W R W Addr 0x0x10244 16 31 Field Reset 0000_0000_0000_0000 R W R W Addr 0x10246 Figure 4 39 Periodic interrupt Timer Count Register PITC Table 4 22 PITC Field Descriptions Bi...

Page 220: ...comparing addresses and a corresponding PCI mask register PCIMSKx 4 3 4 1 PCI Base Register PCIBRx Figure 4 41 shows the PCI base register Figure 4 41 PCI Base Registers PCIBRx Table 4 23 PITR Field...

Page 221: ...16 BA Base Address The upper 17 bits of each base address register are compared to the address on the 60x bus address bus to determine if the access should be claimed by the PCI bridge Used with PCIM...

Page 222: ...L_A19 PCI_IDSEL L_A20 PCI_PERR L_A21 PCI_SERR L_A22 PCI_REQ0 L_A23 PCI_REQ1 L_A24 PCI_GNT0 L_A25 PCI_GNT1 L_A26 PCI_CLK L_A27 CORE_SRESET PCI_RST L_A28 PCI_INTA L_A29 PCI_REQ2 L_A30 AD 0 31 LCL_D 0 3...

Page 223: ...The PowerQUICC II can detect an external assertion of HRESET only if it occurs while the PowerQUICC II is not asserting reset During HRESET SRESET is asserted HRESET is an open collector pin Soft res...

Page 224: ...5 4 Reset Configuration explains the configuration sequence and the terms configuration master and configuration slave Directly after the negation of PORESET and choice of the reset operation mode as...

Page 225: ...4 SRESET Flow The SRESET flow may be initiated externally by asserting SRESET or internally when the chip detects a cause to assert SRESET In both cases the chip asserts SRESET for 512 input clock cy...

Page 226: ...urred 27 CSRS Check stop reset status When the core enters a checkstop state and the checkstop reset is enabled by the RMR CSRE CSRS is set and it remains set until software clears it CSRS is cleared...

Page 227: ...et event is detected ESRS is set and it remains that way until software clears it ESRS is cleared by writing a 1 to it writing zero has no effect 0 No external soft reset event has occurred 1 An exter...

Page 228: ...system typically reads the various configuration words from EPROM in the system and uses them to configure itself as well as the configuration slaves How the PowerQUICC II acts during reset configura...

Page 229: ...on D 0 31 as its configuration word In this way the configuration master continues to configure all PowerQUICC II chips in the system The configuration master always reads eight configuration words r...

Page 230: ...abled In this mode the PowerQUICC II functions as a slave 3 EBM1 External bus mode Defines the initial value of BCR EBM See Section 4 3 2 1 Bus Configuration Register BCR 4 5 BPS Boot port size Define...

Page 231: ...PPC1 Address parity pin configuration Defines the initial value of SIUMCR APPC See Section 4 3 2 6 SIU Module Configuration Register SIUMCR 24 25 CS10PC1 CS10 pin configuration Defines the initial val...

Page 232: ...shown in Figure 5 5 The PowerQUICC II does not access the boot EPROM it is assumed that the default configuration is used upon exiting hard reset Figure 5 5 Single Chip with Default Configuration 5 4...

Page 233: ...ently configuration is done by assigning one configuration master and multiple configuration slaves The PowerQUICC II that controls the boot EPROM should be the configuration master RSTCONF tied to GN...

Page 234: ...other configuration words and drives them to the configuration slaves by asserting RSTCONF As Figure 5 7 PORESET PORESET PORESET PORESET A0 A1 A6 HRESET HRESET HRESET HRESET VCC Configuration Master C...

Page 235: ...t controlled by an PowerQUICC II If this occurs the user must do one of the following Accept the default configuration Emulate the configuration master actions in external logic where the PowerQUICC I...

Page 236: ...Reset MPC8260 PowerQUICC II Family Reference Manual Rev 2 5 14 Freescale Semiconductor...

Page 237: ...UICC II Chapter 9 PCI Bridge describes how the PCI bridge enables the PowerQUICC II to gluelessly bridge PCI agents to a host processor that implements the PowerPC architecture and how it is compliant...

Page 238: ...l number 0b0 Prefix to denote binary number REG FIELD Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text Specific bits fields or numerical ranges appear in brack...

Page 239: ...grated circuit IDL Inter chip digital link IEEE Institute of Electrical and Electronics Engineers IrDA Infrared Data Association ISDN Integrated services digital network JTAG Joint Test Action Group L...

Page 240: ...nagement controller SNA Systems network architecture SPI Serial peripheral interface SPR Special purpose register SRAM Static random access memory TDM Time division multiplexed TLB Translation lookasi...

Page 241: ...II signals grouped by function Note that many signals are multiplexed and this figure does not indicate how these signals are multiplexed NOTE A bar over a signal name indicates that the signal is ac...

Page 242: ..._INTA1 L_A29 1 1 ARTRY PCI_REQ21 L_A30 1 1 DBG DLLOUT1 L_A31 1 1 DBB IRQ3 PCI_AD 31 0 1 LCL_D 0 31 32 64 D 0 63 PCI_C BE 3 0 1 LCL_DP 0 3 4 1 NC DP0 RSRV EXT_BR2 1 IRQ1 DP1 EXT_BG2 1 IRQ2 DP2 TLBISYNC...

Page 243: ...respond to the address bus tenure as required snoop if enabled access internal PowerQUICC II resources memory controller support A 0 31 60x address bus These are input output pins When the PowerQUICC...

Page 244: ...al master should assert this pin to request 60x bus ownership from the internal arbiter IRQ1 DP 1 EXT_BG2 Interrupt request 1 This input is one of the eight external lines that can request by means of...

Page 245: ...branch to its reset vector External bus grant 3 Output The PowerQUICC II asserts this pin to grant 60x bus ownership to an external bus master IRQ5 DP 5 TBEN EXT_DBG3 Interrupt request 5 This input i...

Page 246: ...A is asserted four times to indicate the transfer of four data beats with the last assertion indicating the termination of the burst transfer TEA Transfer error acknowledge Input output Assertion of t...

Page 247: ...er the user should qualify this signal with the bus grant input to the PowerQUICC II before connecting it to the L2 cache Burst address 31 There are five burst address output of the 60x memory control...

Page 248: ...ct byte lanes for write operations 60x bus SDRAM DQM The DQM pins are outputs of the SDRAM control machine These pins select specific byte lanes of SDRAM devices 60x bus UPM byte select The byte selec...

Page 249: ...f the Local bus GPCM These pins select specific byte lanes for write operations Local bus SDRAM DQM The DQM pins are outputs of the SDRAM control machine These pins select specific byte lanes of SDRAM...

Page 250: ...ck circuits LGTA LUPMWAIT LGPL4 LPBS Local bus GPCM TA This input pin is used for transaction termination during GPCM operation Requires external pull up resistor for proper operation Local bus UPM wa...

Page 251: ...ckstop output Output Assertion of CKSTOP_OUT indicates the core is in checkstop mode L_A18 PCI_STOP1 Local bus address 18 Local bus address bit 18 output pin In the local address bus bit 14 is most si...

Page 252: ...when the PowerQUICC II s internal PCI arbiter is not used this pin is used for the Hot Swap interface to connect to the ejector switch logic 0 Switch is closed 1 Switch is open Important note When fu...

Page 253: ...address bus bit 14 is most significant and bit 31 is least significant PCI INTA output When the PowerQUICC II is an agent of the PCI system this pin is an output used by the PowerQUICC II to signal a...

Page 254: ...t This is an output driven from PowerQUICC II s internal interrupt controller Assertion of this output indicates that an unmasked interrupt is pending in PowerQUICC II s internal interrupt controller...

Page 255: ...lect 1 The bank select outputs are used for selecting SDRAM bank when the PowerQUICC II is in 60x compatible bus mode MODCK3 AP 3 TC 2 BNKSEL 2 MODCK3 Clock mode input Defines the operating mode of in...

Page 256: ...tiplexing is described in Chapter 40 Parallel I O Ports PD 4 31 General purpose I O port D bits 4 31 CPM port multiplexing is described in Chapter 40 Parallel I O Ports Power Supply VDD This is the po...

Page 257: ...ls These signals indicate that a bus master has begun a transaction on the address bus Address transfer signals address bus These signals are used to transfer the address Transfer attribute signals Th...

Page 258: ...s in greater detail both in terms of their function and how groups of signals interact Bus Request BR Bus Grant BG Address Bus Busy ABB Transfer Start TS Address Parity AP 0 3 Transfer Size TSIZ 0 3 T...

Page 259: ...cle does not occur if the PowerQUICC II is parked and the address bus is idle BG asserted and ABB input negated Negation Occurs for at least one cycle following a qualified BG even if another transact...

Page 260: ...BG again until the cycle after AACK Negation May occur whenever the PowerQUICC II must be prevented from using the address bus The PowerQUICC II may still assume address bus ownership on the cycle BG...

Page 261: ...us Busy ABB Input Following are the state meaning and timing comments for the ABB input signal State Meaning Asserted Indicates that external device is the address bus master Negated Indicates that th...

Page 262: ...Timing Comments Assertion Negation Must be asserted for one cycle only and then immediately negated Assertion may occur at any time during the assertion of ABB 7 2 3 Address Transfer Signals In intern...

Page 263: ...ription of TT 0 4 signals and transfer type encoding see Section 8 4 3 1 Transfer Type Signal TT 0 4 Encoding 7 2 4 1 1 Transfer Type TT 0 4 Output Following are the state meaning and timing comments...

Page 264: ...4 4 1 Global GBL Output Following are the state meaning and timing comments for the GBL output signal State Meaning Asserted Indicates that the transaction is global and should be snooped by other dev...

Page 265: ...ignals are used to indicate either that the address phase of the transaction has completed successfully or must be repeated and when it should be terminated For detailed information about how these si...

Page 266: ...ss tenure to be retried Timing Comments Assertion Asserted the third bus cycle following the assertion of TS if a retry is required Negation Occurs the second bus cycle after the assertion of AACK Sin...

Page 267: ...and timing comments for DBG State Meaning Asserted Indicates that the PowerQUICC II may with the proper qualification assume mastership of the data bus The PowerQUICC II derives a qualified data bus...

Page 268: ...le following the assertion of the final TA following TEA or certain ARTRY cases High Impedance Occurs after DBB is negated 7 2 6 2 2 Data Bus Busy DBB Input Following are the state meaning and timing...

Page 269: ...bursts transitions on the bus clock cycle following each assertion of TA and for port size transitions on the bus clock cycle following each assertion of PSDVAL High Impedance Occurs on the bus clock...

Page 270: ...ansfer Termination Signals Data termination signals are required after each data beat in a data transfer Note that in a single beat transaction that is not a port size transfer the data termination si...

Page 271: ...one bus clock cycle and then negate it to advance the burst transfer to the next beat and insert wait states during the next beat Note when configured for 1 1 clock mode and is performing a burst read...

Page 272: ...gation of DBB 7 2 8 2 2 Transfer Error Acknowledge TEA Output Following are the state meaning and timing comments for the TEA output State Meaning Asserted Indicates that a bus error has occurred Asse...

Page 273: ...gate it to insert wait states during the next beat Note when the PowerQUICC II Processor is configured for 1 1 clock mode and is performing a burst read into the data cache the PowerQUICC II requires...

Page 274: ...60x Signals MPC8260 PowerQUICC II Family Reference Manual Rev 2 7 18 Freescale Semiconductor...

Page 275: ...ately but signals the memory system that it is attempting an atomic operation If the operation fails status is kept so that PowerQUICC II can try again Beat A single state on the PowerQUICC II interfa...

Page 276: ...Granting potential bus mastership without requiring a bus request from that device This eliminates the arbitration delay associated with the bus request Pipelining Initiating a bus transaction before...

Page 277: ...enure timing 8 2 2 60x Compatible Bus Mode The 60x compatible bus mode can include one or more potential external masters for example an L2 cache an ASIC DMA a high end processor that implements the P...

Page 278: ...and termination as shown in Figure 8 3 The independence of the tenures is indicated by showing the data tenure overlap the next address tenure which allows split bus transactions to be implemented at...

Page 279: ...ta tenure Arbitration After the address tenure begins the bus device arbitrates for data bus mastership Transfer After the device is granted data bus mastership it samples the data bus for read operat...

Page 280: ...RTRY are negated DBB data bus busy Assertion by the device indicates that the device is the current data bus master The device master always assumes data bus mastership if it needs the data bus and is...

Page 281: ...receiving BG In addition to the external signals there are internal request and grant signals for the PowerQUICC II processor communications processor refresh controller and the PCI internal bridge Bu...

Page 282: ...en a replacement copyback transaction waiting to be run on the bus is killed by a snoop of another bus master This can also occur when the reservation set by a pending stwcx transaction is cancelled b...

Page 283: ...4 transfer code TC 0 2 transfer size TSIZ 0 3 and transfer burst TBST signals These signals are discussed in the following sections 8 4 3 1 Transfer Type Signal TT 0 4 Encoding The transfer type sign...

Page 284: ...ACK is asserted 10000 eieio Address only Address only if enabled eieio if enabled Not applicable Assert AACK BG is negated until PowerQUICC II buffers are flushed 101 00 Graphics write Single beat wri...

Page 285: ...able Not applicable Illegal 11010 Read atomic Single beat read or burst Single beat read lwarx CI load Clean or flush Read assert AACK and TA 11110 Read with intent to modify atomic Burst Burst lwarx...

Page 286: ...tion about the corresponding address mainly regarding the source of the transaction Note that TCx signals can be used with the TT 0 4 and TBST to further define the current transaction 8 4 3 3 TBST an...

Page 287: ...d zero double word first However because burst reads are performed critical double word first a burst read transfer may not start with the first double word of the cache block and the cache block fill...

Page 288: ...Transfer Double Word Starting Address A 27 28 001 1 A 27 28 specifies the first double word of the 32 byte block being transferred any subsequent double words must wrap around the block A 29 31 are a...

Page 289: ...nslation logic can generate substantial exception overhead when the load store multiple and load store string instructions access misaligned data It is strongly recommended that software attempt to al...

Page 290: ...port must reside on bits D 0 15 and an 8 bit port must reside on bits D 0 7 The PowerQUICC II always tries to transfer the maximum amount of data on all bus cycles for a word operation it always assum...

Page 291: ...erent Port Size Devices 0 31 63 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 D 0 7 D 8 15 D 15 23 D 24 31 D 32 39 D 40 47 D 48 55 D 56 63 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP0 OP1 OP2...

Page 292: ...5 56 63 0 7 8 15 16 23 24 31 0 7 8 15 0 7 Byte 0001 000 OP0 2 2 OPn These lanes are read or written during that bus transaction OP0 is the most significant byte of a word operand and OP7 is the least...

Page 293: ...5 6 7 Table 8 9 Address and Size State Calculations Size State Address State 0 4 Port Size Next Size State Next Address State 0 4 Byte x x x x x x Stop 2 Byte x x x x 0 Byte Byte x x x x 1 x x 0 0 1 B...

Page 294: ...tate machine Only extended transfers use these states Table 8 10 Data Bus Contents for Extended Write Cycles Transfer Size TSIZ 0 3 Address State A 29 31 External Data Bus Pattern D 0 7 D 8 15 D 16 23...

Page 295: ...1 x x 0 1 0 Half Byte x x 1 0 0 x x 1 0 0 x x 1 1 0 Word x x 0 0 1 Byte 3 Byte x x 0 1 0 x x 0 1 1 x x 1 0 0 5 Byte x x 0 0 0 Byte Word x x 0 0 1 x x 0 0 1 x x 0 1 0 x x 0 1 0 x x 0 1 1 x x 0 1 1 x x...

Page 296: ...of one to its internal slaves 8 4 4 1 Address Retried with ARTRY The address transfer can be terminated with the requirement to retry if ARTRY is asserted during the address tenure and through the cy...

Page 297: ...nd the entire transaction is rerun This retry mechanism allows the memory system to begin operating in parallel with the bus snoopers provided external devices do not present data sooner than the bus...

Page 298: ...control the 60x bus pipeline condition To maintain the one level pipeline AACK is not asserted for a pipelined address tenure until the current data tenure ends The PowerQUICC II also delays asserting...

Page 299: ...nals are not asserted if the data bus which is shared with memory is busy with a transaction A qualified data bus grant QDBG can be expressed as the assertion of DBG while DBB and ARTRY associated wit...

Page 300: ...erQUICC II for which data streaming mode is enabled may leave DBB asserted after the last TA of a transaction and this is a violation of the strict bus protocol The data streaming mode is enabled by s...

Page 301: ...f AACK 8 5 5 Port Size Data Bus Transfers and PSDVAL Termination The PowerQUICC II can transfer data via data ports of 8 16 32 and 64 bits as shown in Section 8 4 3 Address Transfer Attribute Signals...

Page 302: ...Figure 8 9 28 Bit Extended Transfer to 32 Bit Port Size Figure 8 10 shows a burst transfer to a 32 bit port Each double word burst beat is divided into two port sized beats such that the four double w...

Page 303: ...single beat or burst transaction This sequence is shown in Figure 8 11 In Figure 8 11 the data bus is busy at the beginning of the transaction thus delaying the assertion of DBG Note that data errors...

Page 304: ...ransaction must be snooped by other snooping devices on the bus Address bus masters assert GBL to indicate that the current transaction is a global access that is an access to memory shared by more th...

Page 305: ...II processor reacts according to the MEI protocol shown in Figure 8 12 This figure assumes that WIM 0b001 memory space is marked for write back caching allowed and coherency enforced modes Figure 8 1...

Page 306: ...execution of an eciwx or ecowx instruction the selected DMA device should assert the PowerQUICC II s TLBISYNC signal and hold it asserted during its DMA tenure if it is using a shared translation add...

Page 307: ...ge are as follows PCI Specification Revision 2 2 compliant and supports frequencies up to 66 MHz On chip arbitration Support for PCI to 60x memory and 60x memory to PCI streaming PCI host bridge or pe...

Page 308: ...CC II Figure 9 2 PCI Bridge Structure PCI 60x 60x to Local G2 Core Bridge Bus Bus PowerQUICC II Mux PCI_MODE 0 1 PCI Bridge SDMA DPRAM Communications Processor Module PCI Interface DMA I2O Regs PCI Bu...

Page 309: ...omatically loads the PCI configuration data from the EPROM immediately following hard reset In addition to the hard reset configuration word the PCI configuration register data should be programmed wi...

Page 310: ...l status register the inbound message interrupt status register and the outbound message interrupt status register For PCI interrupt vector calculation refer to Section 4 2 4 Interrupt Vector Generati...

Page 311: ...on PICMG 2 1 R1 0 August 3 1998 9 9 PCI Interface The PCI bridge connects the processor and memory system to the I O components via the PCI system bus This interface acts as both initiator master and...

Page 312: ...Bus Commands PCI bus commands indicate the type of transaction occurring on the bus These commands are encoded on PCI_C BE 3 0 during the address phase of the transaction PCI bus commands are describe...

Page 313: ...read from prefetchable space when seen as a target fetches a cache line of data 32 bytes from the starting address even though all 32 bytes may not actually be sent to the initiator 0b0111 Memory writ...

Page 314: ...saction with each agent responsible for its own address decode The information contained in the two lower address bits AD1 and AD0 depends on the address space In the I O address space all 32 address...

Page 315: ...nd AD 31 0 use the idle cycle between transactions as their turnaround cycle An idle cycle in PCI is when both FRAME and IRDY are negated Byte lanes not involved in the current data transfer are drive...

Page 316: ...fast DEVSEL assertion The earliest the target can provide valid data is one cycle after the turnaround cycle The target must drive the AD 31 0 signals when DEVSEL is asserted The data phase completes...

Page 317: ...ions end when FRAME and IRDY are both negated indicating the idle cycle The PCI bridge as an initiator terminates a transaction when FRAMEis negated and IRDY is asserted This indicates that the final...

Page 318: ...ore data is transferred and the initiator therefore does not have to wait for a final data transfer see the retry diagram in Figure 9 7 Figure 9 7 Target Initiated Terminations Note that when an initi...

Page 319: ...ime Target abort refers to the abnormal termination that is used when a fatal error has occurred or when a target will never be able to respond Target abort is indicated by the fact that STOP is asser...

Page 320: ...or PCI transactions to and from prefetchable memory In other words when the PCI bridge is a target for a PCI initiated transaction it supplies or accepts multiple cache lines of data without disconnec...

Page 321: ...determining when accesses to CONFIG_DATA should be translated to configuration cycles There are two types of translations supported Type 0 translations For when the device is on the PCI bus connected...

Page 322: ...to remote host generated PCI configuration accesses to the PCI interface This is indicated by decoding the configuration command along with the PCI bridge s IDSEL being asserted A remote host can acce...

Page 323: ...nable lines during the address phase During the address phase AD 31 0 do not contain a valid address but are driven with stable data and valid parity PAR During the data phase the byte enable signals...

Page 324: ...status register If a data parity error occurs on a read transaction the PCI bridge aborts the transaction internally As a target the PCI bridge completes the transaction on the PCI bus even if a data...

Page 325: ...ing reset the PCI bridge samples the PCI_CFG 1 pin and programs the PCI_ARB_DIS bit accordingly to determine if the arbiter is enabled or disabled The arbiter can also be enabled or disabled by direct...

Page 326: ...of N 1 bus transactions If all devices are programmed to the same priority level or if there is only one device at the low priority the algorithm provides each device an equal number of bus grants in...

Page 327: ...anslation window the transaction is sent to the PCI bus with no address translation as a PCI memory transaction to non prefetchable space An address decode flow chart for transactions from the 60x bus...

Page 328: ...ddress This way the PCI master can access any of the PCI bridge registers DMA MU etc without wasting an inbound translation window In effect it suggests that we have a total of three inbound windows 2...

Page 329: ...by the DMA controller or message unit fall into one of the following cases If the transaction address is within one of the outbound PCI translation windows the transaction is sent to the PCI bus with...

Page 330: ...or the same bus should not overlap This means that a situation where an inbound window translation points back into an outbound window or a situation where an outbound translation window points back i...

Page 331: ...R PCI inbound comparison mask register which are located in the PCI bridge s PCI internal register space Figure 9 15 shows an example translation window for inbound memory accesses Figure 9 15 Inbound...

Page 332: ...ion registers allow three simultaneous translation windows Software can move and adjust the host memory window translations and sizes during run time This allows software to access host memory or to a...

Page 333: ...ion registers are not guaranteed to have predictable values Software must preserve the values of reserved bits when writing to a configuration register Also when reading from a configuration register...

Page 334: ...control register MUCR R W 0x0000_0002 9 12 3 4 7 9 83 0x104F0 Queue base address register QBAR R W 0x0000_0000 9 12 3 4 8 9 84 0x10500 DMA 0 mode register DMAMR0 R W 0x0000_0000 9 13 1 6 1 9 88 0x105...

Page 335: ...OCMR0 R W 0x0000_0000 9 11 1 5 9 31 0x10818 PCI outbound translation address register 1 POTAR1 R W 0x0000_0000 9 11 1 3 9 30 0x10820 PCI outbound base address register 1 POBAR1 R W 0x0000_0000 9 11 1...

Page 336: ...9 10 2 2 PCI Outbound Translation Figure 9 17 PCI Outbound Translation Address Registers POTARx Table 9 4 describes POTARx 0x108E0 PCI inbound comparison mask register 1 PICMR1 R W 0x0000_0000 9 11 1...

Page 337: ...ithout translation to the 60x bus see Figure 9 13 9 11 1 5 PCI Outbound Comparison Mask Registers POCMRx The PCI outbound comparison mask registers POCMRx shown in Figure 9 19 defines the window size...

Page 338: ...This bit indicates that the translation is to PCI memory or PCI I O space 0 PCI memory 1 PCI I O 29 Prefetchable This bit indicates that the address space is prefetchable so streaming can occur 0 not...

Page 339: ...scard timer enable 0 Disable the discard timer 1 Enable the discard timer 30 24 Reserved 23 0 Preload timer value Preload value for 24 bit discard timer Delayed PCI read transactions to a non prefetch...

Page 340: ...bridge can have higher priorities than other masters The breaks are inserted only if some other 60x bus master requests the bus The user should find the optimum setting by testing arriving at the best...

Page 341: ...rresponding error condition is captured Each bit is cleared by writing a one 12 1 Reserved should be cleared 0 LE_MODE Little endian mode Controls the translation of 60x PCI and PCI 60x Refer to Secti...

Page 342: ...n in the inbound posted I2O queue An overflow condition in the outbound free I2O queue These two interrupts can be masked in the I2O unit 11 NMI General error interrupt indication In host mode this bi...

Page 343: ...error 1 PCI_DATA_PAR_WR PCI write data parity error 0 PCI_ADDR_PAR PCI address parity error read or write 31 16 Field Reset 0000_0000_0000_0000 R W R W Addr 0x1088A 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 344: ...rQUICC II sinks PERR This error is only a function of data 6 PCI_PERR_RD PCI parity error received on a read The PowerQUICC II sinks PERR This error is only a function of data 5 PCI_SERR PCI SERR rece...

Page 345: ...terrupt 1 ESR I2O_DBMC if enabled causes a machine check 11 NMI General error interrupt indication 10 IRA Illegal register access with incorrect size 9 I2O_IPQO I2O inbound post queue overflow 8 I2O_O...

Page 346: ...1 14 PCI Error Control Capture Register PCI_ECCR The PCI error control capture register PCI_ECCR shown in Figure 9 28 stores information associated with the first PCI error captured Table 9 13 PCI_EAC...

Page 347: ...in Table 9 10 For example a value of 0b101 indicates a PCI SERR received condition while a value of 0b010 indicates a PCI read data parity error 27 24 Beat number 32 bit data beat number for data par...

Page 348: ...ese registers are tied to the GPLABARx registers see Section 9 11 2 14 General Purpose Local Access Base Address Registers GPLABARx A change 1 Parity bit Parity bit for PCI bus data word 0 Valid info...

Page 349: ...arison mask registers PICMRx shown in Figure 9 31 defines the inbound window s size In PCI agent mode this register should be initialized either by the core or by the CP s automatic EPROM load before...

Page 350: ...that do not need to maintain coherency on system memory accesses by PCI 0 Snooping is enabled 1 Snooping is disabled 29 Prefetchable Indicates whether the address space is prefetchable so that streami...

Page 351: ...on Registers on page 9 64 Table 9 19 PCI Bridge PCI Configuration Registers Address offset Register Access Reset Section Page 00 Vendor ID R 0x1057 9 11 2 1 9 46 02 Device ID R 0x18C0 9 11 2 2 9 47 04...

Page 352: ...2 20 9 57 3F MAX LAT R 0x00 9 11 2 21 9 58 40 Reserved 44 PCI function R W 0x0000 9 11 2 22 9 58 46 PCI arbiter control register R W Mode dependent 9 11 2 23 9 59 48 Hot swap register block R W 0x00nn...

Page 353: ...lity to generate and respond to PCI cycles Figure 9 35 PCI Bus Command Register 15 0 Field VID Reset 0001_0000_0101_0111 R W R Addr 0x00 Table 9 20 Vendor ID Register Description Bits Name Description...

Page 354: ...whether the PCI bridge responds to parity errors on the PCI bus 0 Parity errors are ignored and normal operation continues 1 Action is taken on a parity error 5 Reserved should be cleared 4 Memory wri...

Page 355: ...ter abort 12 Received target abort Set whenever a PCI bridge initiated transaction on the PCI bus is terminated by a target abort 11 Signaled target abort Set whenever the PCI bridge acting as the PCI...

Page 356: ...Table 9 24 R W R Addr 0x08 Table 9 24 Revision ID Register Description Bits Name Reset Value Description 7 0 Revision ID Revision Dependent Specifies a device specific revision code for the PowerQUIC...

Page 357: ...te that the I2O support is not fully standard compliant 9 11 2 9 PCI Bus Cache Line Size Register Figure 9 41 and Table 9 28 describe the PCI bus cache line size register 7 0 Field SC Reset 0000_0000...

Page 358: ...f the system in terms of 32 bit words eight 32 bit words 32 bytes This register is read write however an attempt to program this register to any value other than 8 results in it being cleared 7 3 2 0...

Page 359: ...o the PowerQUICC II s internal memory mapped registers Transactions from PCI that hit the PIMMRBAR are translated to the IMMR and sent to the logic that controls the internal memory mapped registers P...

Page 360: ...only to the bits allowed by the PICMRx mask Similarly a write to PIBARx causes a write to GPLABARx of the non masked bits of the base address GPLABARx is shown in Figure 9 46 31 17 16 Field BA BA Rese...

Page 361: ...R1 Table 9 33 GPLABARx Field Descriptions Bits Name Description 31 12 Base address Represents the base address for the inbound GPLA memory window The number of upper bits that the PCI bridge allows to...

Page 362: ...scribes the PCI bus interrupt line register Table 9 34 Subsystem Vendor ID Register Description Bits Name Description 15 0 Vendor ID Identifies the add in board or subsystem where the PCI device resid...

Page 363: ...t 0000_0000 R W R W Addr 0x3C Table 9 37 PCI Bus Interrupt Line Register Description Bits Name Description 7 0 Interrupt line Contains the interrupt routing information Software can use this register...

Page 364: ...lds Table 9 39 PCI Bus MIN GNT Description Bits Name Description 7 0 MIN GNT Specifies the length of the device s burst period The value 0x00 indicates that the PCI bridge has no major requirements fo...

Page 365: ...CI side when the device is in host mode therefore this bit applies only for the internal memory mapped configuration space 0 PCI bridge accepts accesses to the internal memory mapped configuration spa...

Page 366: ...r The PCI bridge presents its request on REQ0 to the external arbiter and receives its grant on GNT0 14 Parking Mode Controls which device receives the bus grant when there are no outstanding bus requ...

Page 367: ...next item in the capabilities linked list A value of 0x00 indicates that this is the last item in the list 7 0 CAP_ID CompactPCI Hot Swap capability ID read only 23 22 21 20 19 18 17 16 Field INS EXT...

Page 368: ...ming an access That is the data appears in the core register in ascending significance byte order LSB to MSB Software loads the configuration register address and the configuration register data into...

Page 369: ...ory so it is stored into the memory region in LE format For the MPC603e and the PowerQUICC II implementations there is NO latency difference associated with lwbrx and stwbrx commands compared to the o...

Page 370: ...as some control information The last data structure entry in the table is marked by setting its Last bit Figure 9 58 Data Structure for Register Initialization Table 9 45 describes the data structure...

Page 371: ...routine 9 12 Message Unit I2O The embedded processor is often part of a larger system containing many processors and distributed memory These processors tend to work on tasks independent of the host...

Page 372: ...ropriate bit in the outbound interrupt status register 9 12 1 1 Inbound Message Registers IMRx The inbound message registers described in Figure 9 60 and Figure 9 46 are accessible from the PCI bus an...

Page 373: ...local processor can write to the outbound register which causes the outbound interrupt signal INTA to assert thus interrupting the remote processor on the PCI bus 9 12 2 1 Outbound Doorbell Register...

Page 374: ...000_0000_0000 R W Refer to Table 9 48 Addr 0x10462 15 0 Field ODRx Reset 0000_0000_0000_0000 R W Refer to Table 9 48 Addr 0x10460 Table 9 48 ODR Field Descriptions Bits Name Access Description 31 29 R...

Page 375: ...ame The messages are located in local system memory Tracking of the status and location of these messages is done with four FIFOs two FIFOs for inbound and two for outbound messages also located in lo...

Page 376: ...ows external PCI masters to post messages to the local processor I2O defines two inbound FIFOs an inbound post FIFO and an inbound free FIFO MFA MFA MFA MFA MFA MFA MFA MFA MFA MFA MFA MFA MFA MFA MFA...

Page 377: ...local processor are posted to the inbound free list FIFO that is pointed to by the inbound free_FIFO head pointer register described in Figure 9 65 and Table 9 50 The local processor is responsible f...

Page 378: ...ble 9 62 The local processor acknowledges the message i e MFA by writing a one to the appropriate status bit IMISR IPQI to clear it The local processor fetches the MFA by reading the contents of the I...

Page 379: ...il Pointer Register IPTPR 31 20 19 16 Field QBA IPHP Reset 0000_0000_0000_0000 R W R R W Addr 0x104B2 15 2 1 0 Field IPHP Reset 0000_0000_0000_0000 R W R W R Addr 0x104B0 Table 9 52 IPHPR Field Descri...

Page 380: ...of a message that was posted in the outbound post FIFO and wants to return the MFA to the free list it writes to OFQPR refer to Section 9 12 3 4 2 Outbound FIFO Queue Port Register OFQPR The PCI bridg...

Page 381: ...t empty head and tail pointers are not equal The outbound post queue interrupt bit is set in the outbound interrupt status register The status bit is cleared when the head and tail pointers are equal...

Page 382: ...for updating this register Figure 9 71 Outbound Post_FIFO Head Pointer Register OPHPR Posted MFAs are picked up by PCI hosts that are pointed to by the outbound post_FIFO tail pointer register descri...

Page 383: ...73 and Table 9 58 Figure 9 73 Inbound FIFO Queue Port Register IFQPR 31 20 19 16 Field QBA OPTP Reset 0000_0000_0000_0000 R W R R W Addr 0x104DA 15 2 1 0 Field OPTP Reset 0000_0000_0000_0000 R W R W...

Page 384: ...I This clears both the interrupt and the corresponding status bit The local processor provokes an outbound message interrupt by writing to either of the two outbound message registers OMR0 or OMR1 OMI...

Page 385: ...I R Outbound post queue interrupt When set indicates that a message or messages are posted in the outbound queue To clear the interrupt software has to read all MFAs in the outbound post FIFO This bit...

Page 386: ...00 R W Refer to Table 9 61 Addr 0x10436 15 6 5 4 3 2 1 0 Field OPQIM ODIM OM1IM OM0IM Reset 0000_0000_0000_0000 R W Refer to Table 9 61 Addr 0x10434 Table 9 61 OMIMR Field Descriptions Bits Name R W D...

Page 387: ...rflow Interrupt When set indicates that the Inbound Post_FIFO Head pointer is equal to the Inbound Post_FIFO Tail pointer and the queue is full A machine check interrupt is generated 6 R Reserved shou...

Page 388: ...000_0000_0000 R W R W Addr 0x10484 Table 9 63 IMIMR Field Descriptions Bits Name Description 31 9 Reserved should be cleared 8 OFOIM Outbound free overflow interrupt mask 0 Outbound free overflow inte...

Page 389: ...it Control Register MUCR Table 9 64 describes MUCR fields 1 IM1IM Inbound message 1 interrupt mask 0 Inbound doorbell interrupt is allowed 1 Inbound doorbell interrupt is masked 0 IM0IM Inbound messag...

Page 390: ...32 Kbytes 00100 16K entries 64 Kbytes 01000 32K entries 128 Kbytes 10000 64K entries 256 Kbytes All others reserved 0 CQE RW Circular queue enable When set will allow PCI masters to access the inboun...

Page 391: ...Interrupt on completed segment chain and error Supports all transfer combinations between 60x memory and PCI memory 60x to 60x PCI to PCI 60x to PCI and PCI to 60x Figure 9 81 shows a block diagram o...

Page 392: ...has occurred Below are the initialization steps of a DMA transfer in direct mode Poll the CB channel busy bit in the status register to make sure the DMA channel is idle refer to Section 9 13 1 6 2 D...

Page 393: ...nfigure the DMA for a new transfer Leave the channel in the halted state When a DMA channel is halted its programming model is completely accessible If the DMA is halted due to an error condition the...

Page 394: ...riting data to 60x memory space beginning at the destination address The process is repeated until there is no more data to transfer or an error condition has occurred while accessing memory 9 13 1 6...

Page 395: ...each transaction when DAHE is enabled The Byte Count Register must be in multiples of the size and the Destination Address Register must be aligned based on the size 00 1 byte 01 2 bytes 10 4 bytes 11...

Page 396: ...alt when a transfer error occurs TE bit is set 2 CTM Channel transfer mode 0 Chaining mode See Section 9 13 1 2 DMA Chaining Mode 1 Direct mode See Section 9 13 1 1 DMA Direct Mode 1 CC Channel contin...

Page 397: ...Write 1 to clear Transfer error This bit is set when there is an error condition during the DMA transfer and the TEM bit is cleared 6 3 R Reserved should be cleared 2 CB Read Only Channel busy When se...

Page 398: ...the address where the DMA controller will be writing data to This address can be in either PCI memory or 60x memory The software has to ensure that this is a valid memory address Table 9 68 DMACDARx...

Page 399: ...transfer size is 64 Mbytes Figure 9 87 DMA Byte Count Register 0 3 DMABCRx Table 9 71 describes DMABCRx fields 31 16 Field DA Reset 0000_0000_0000_0000 R W R W Addr 0x1051A DMAADAR0 0x1059A DMAADAR1 0...

Page 400: ...register is decremented after each DMA read operation 31 16 Field NDA Reset 0000_0000_0000_0000 R W R W Addr 0x10526 DMANDAR0 0x105A6 DMANDAR1 0x10626 DMANDAR2 0x106A6 DMANDAR3 15 5 4 3 2 1 0 Field ND...

Page 401: ...Contains the source address of the DMA transfer After the DMA controller reads the descriptor from memory this field will be loaded into the source address register For the bit definition refer to Sec...

Page 402: ...788aabbccdd double word double c 0x8765432101234567 double word double d 0x0123456789abcdef double word Descriptor Results Source Address 0x44332211 MSB LSB Destination Address 0x88776655 MSB LSB Next...

Page 403: ...errupt conditions Errors detected by the PCI bridge are reported by asserting internal error signals for each detected error The system error SERR and parity error PERR signals are used to report erro...

Page 404: ...ta parity error Bit 6 of the PCI command register controls whether the PCI bridge ignores PERR 9 14 1 1 3 Error Reporting The error signals generated by the PCI bridge indicate which specific error ha...

Page 405: ...e PCI target by asserting PERR and tries to complete the command if possible The PCI bridge also sets bit 15 of the PCI status register regardless of the value of the parity error response bit bit 6 i...

Page 406: ...utilities errors are errors detected in the I2O interface Embedded utilities errors are limited to queue overflows in the I2O outbound free queue and the inbound post queue 9 14 1 4 1 Outbound Free Qu...

Page 407: ...local bus frequencies The main PLL can multiply the frequency of the input clock to the final CPM frequency 10 1 Clock Unit The PowerQUICC II s clock module consists of the input clock interface OSCM...

Page 408: ...r DFBRG Division factor for the BRGCLK These fields are described in detail in Section 10 8 System Clock Control Register SCCR and Section 10 9 System Clock Mode Register SCMR Figure 10 1 System PLL B...

Page 409: ...C8265 and the MPC8266 The PCI bridge uses a PLL and a DLL for clocking The PLL is used for generating a high speed clock from CLKIN1 for the chip s logic blocks and the DLL is used for de skewing the...

Page 410: ...PCI bus clock The PCI bus clock is then driven by the DLL circuit to the DLLOUT pin which has a feedback path from the board to the CLKIN2 pin This feedback is used to control the clock skew in order...

Page 411: ...e number between 1 and 16 The delay is the same for all dividers independent on the programmable number so the clocks are synchronized The output of each divider has two phases one shifted 90 from the...

Page 412: ...be kept short and direct VCCSYN Drain voltage Analog VDD dedicated to analog main PLL circuits To ensure internal clock stability filter the power to the VCCSYN input with a circuit similar to the one...

Page 413: ...Factor MF If the ratio of CPM_CLK CLKIN is an integer A MF A If CPM_CLK CLKIN is A 5 MF 2 x A 5 For example if CPM_CLK CLKIN is 166 66 MHz 66 66 MHz 2 5 then MF 5 The relevant factors are as follows...

Page 414: ...24 25 28 29 30 31 Field PCI_MODE1 1 MPC8250 MPC8265 and MPC8266 only PCI_MODCK1 PCIDF1 CLPD DFBRG Reset 0 0 01 R W R W R R W Addr 0x10C82 Figure 10 5 System Clock Control Register SCCR Table 10 2 SCCR...

Page 415: ...n the core does This may be useful for debug tools that use the assertion of QREQ as an indication of breakpoint in the core Note When the core is disabled CLPD must be cleared 30 31 DFBRG 01 Unaffect...

Page 416: ...factor This value is always 1 16 18 Reserved 19 PLLDF Config pins Unaffected PLL pre divider factor Ensures that PLLMF is an integer value regardless of whether the ratio CPM_CLK CLKIN is an integer...

Page 417: ...value is equal to the internal supply For more information refer to Section 1 2 Electrical and Thermal Characteristics in the hardware specifications document available at wwww freescale com Table 10...

Page 418: ...n PLL is working core PLL is stopped and internal clocks are disabled When stop mode is entered software sets the sleep bit in the core HID0 10 1 and the clock block freezes all clocks to the chip the...

Page 419: ...s interface to DRAMs burstable SRAMs and almost any other kind of peripheral The refresh timers allow refresh cycles to be initiated The UPM can be used to generate different timing patterns for the c...

Page 420: ...the 60x bus and the local bus Flexible UPM assignment The user can assign any of the three UPMs to the 60x bus or the Local bus Figure 11 1 shows the dual bus architecture Figure 11 1 Dual Bus Archite...

Page 421: ...etup time for synchronous devices Synchronous DRAM machine 60x or local bus Provides the control functions and signals for glueless connection to JEDEC compliant SDRAM devices Back to back page mode f...

Page 422: ...lexing for all on chip bus masters supporting 64 128 256 and 512 Kbyte and 1 2 4 8 16 32 64 128 256 Mbyte page banks 11 2 Basic Architecture The memory controller consists of three basic machines Sync...

Page 423: ...ated and checked for any memory bank with a 64 bit port size Each memory bank can be selected for read only or read write operation Each memory bank can use data pipelining which reduces the required...

Page 424: ...SH device The chip select allows 0 to 30 wait states The UPMs provide a flexible interface to many types of memory devices Each UPM can control the address multiplexing for accessing DRAM devices and...

Page 425: ...and ORx for that bank are used to control the memory access If a match is found in more than one bank the lowest numbered bank handles the memory access that is bank 0 has priority over bank 1 NOTE A...

Page 426: ...ode This is done by setting BCR ETM BCR LETM for the local bus Refer to Section 4 3 2 1 Bus Configuration Register BCR NOTE RMW Parity and ECC Modes and Pipelined Addresses The following applies only...

Page 427: ...internal or external While the bus is locked no other device can be granted the bus The lock is released when the master that created the lock accesses the same bank with a read transaction If the mas...

Page 428: ...erQUICC II the memory controller handles the port size data checking atomic locking and data pipelining as if the access were governed by it This feature allows multiple PowerQUICC II systems to be co...

Page 429: ...troller accumulates PSDVAL assertions and when a double word or the transfer size is transferred the memory controller asserts TA to indicate that a 60x data beat was transferred Table 11 1 shows the...

Page 430: ...DR 29 N C N C N C Connected Connected Connected BADDR 30 N C N C N C N C Connected Connected BADDR 31 N C N C N C N C N C Connected Table 11 3 60x Bus Memory Controller Registers Abbreviation Name Ref...

Page 431: ...12 BR2 0x1011A BR3 0x10122 BR4 0x1012A BR5 0x10132 BR6 0x1013A BR7 0x10142 BR8 0x1014A BR9 0x10152 BR10 0x1015A BR11 1 For BR0 these fields depend on reset configuration sequence See Section 5 4 1 Har...

Page 432: ...mory controller bank is not used for atomic operations 01 Read after write atomic RAWA Writes to the address space handled by the memory controller bank cause the PowerQUICC II to lock the bus for the...

Page 433: ...ee Section 11 4 12 SDRAM Configuration Examples 0 11 12 15 Field SDAM LSDAM Reset 0000_0000_0000_00001 R W R W Addr 0x0x10104 OR0 0x0x1010C OR1 0x0x10114 OR2 0x0x1011C OR3 0x0x10124 OR4 0x0x1012C OR5...

Page 434: ..._1100 4 Mbytes 1111_1111_1110 2 Mbytes 1111_1111_1111 1 Mbyte Note If xSDMR PBI 0 the maximum size of the memory bank should not exceed 128 Mbytes 12 16 LSDAM Lower SDRAM address mask Clearing LSDAM i...

Page 435: ...13C OR7 0x0x10144 OR8 0x0x1014C OR9 0x0x10154 OR10 0x0x1015C OR11 16 17 18 19 20 21 22 23 24 27 28 29 30 31 Field AM BCTLD CSNT ACS SCY SETA TRLX EHTR Reset1 0 00 0 1 11 0 1111 0 1 0 0 R W R W Addr 0x...

Page 436: ...ng attribute settings The total memory access length is 2 SCY x Clocks If the user selects an external PSDVAL response for this memory bank by setting the SETA bit write a non zero values to SCY 0000...

Page 437: ...R4 0x1012E OR5 0x10136 OR6 0x1013E OR7 0x10146 OR8 0x1014E OR9 0x10156 OR10 0x1015E OR11 1 Reset values are for OR0 only OR1 11 are undefined at reset Figure 11 9 ORx UPM Mode Table 11 7 Option Regist...

Page 438: ...hold time on read accesses Indicates how many cycles are inserted between a read access from the current bank and the next access 00 Normal timing is generated by the memory controller No additional...

Page 439: ...fect on the 60x bus or the SDRAM port size is 8 16 or the SDRAM is connected to the BADDR lines not needed for 64 32 port size the bus master must supply the mode register data on the low bits of the...

Page 440: ...iming for READ WRITE command after an ACTIVATE command See Section 11 4 6 2 Activate to Read Write Interval 001 1 clock cycle 010 2 clock cycles 111 7 clock cycles 000 8 clock cycles 23 BL Burst lengt...

Page 441: ...e control lines going to both the SDRAM and address lines setting BUFCMD causes all SDRAM control lines except CS to be asserted for two cycles instead of one See Section 11 4 6 8 External Address and...

Page 442: ...Address Multiplexing SDAM and BSMA 8 10 BSMA Bank select multiplexed address line Selects which PowerQUICC II address pins serve as bank select address for the local bus SDRAM See Section 11 4 5 2 SD...

Page 443: ...TTORW Activate to read write interval Defines the earliest timing for READ WRITE command after an ACTIVATE command See Section 11 4 6 2 Activate to Read Write Interval 001 1 clock cycle 010 2 clock cy...

Page 444: ...e placed on the control lines going to both the SDRAM and address lines setting BUFCMD causes all SDRAM control lines except CS to be asserted for two cycles instead of one See Section 11 4 6 8 Extern...

Page 445: ...next memory access that hits a UPM assigned bank read the contents of the RAM location pointed by MAD into the MDR After the access the MAD field is automatically incremented 11 Run pattern On the nex...

Page 446: ...After a system reset GPL_x4DIS 1 14 17 RLFx Read loop field Determines the number of times a loop defined in the UPMx will be executed for a burst or single beat read pattern or when MxMR OP 11 RUN co...

Page 447: ...W Addr 0x0x10188 16 31 Field MD Reset xxxx_xxxx_xxxx_xxxx1 R W R W Addr 0x1018A 1 Undefined at reset Figure 11 12 Memory Data Register MDR Table 11 11 MDR Field Descriptions Bits Name Description 0 31...

Page 448: ...4 60x Bus Assigned UPM Refresh Timer PURT Table 11 13 60x Bus Assigned UPM Refresh Timer PURT Bits Name Description 0 7 PURT Refresh timer period Determines the timer period according to the following...

Page 449: ...le For a 25 MHz system clock and a required service rate of 15 6 s given MPTPR PTP 31 the LURT value should be 11 decimal 12 32 25 MHz 15 36 s which is less than the required service period of 15 6 s...

Page 450: ...assigned to the local bus and is refresh enabled LSDMR RFEN 1 Each time the timer expires all banks that qualify generate a bank staggering auto refresh request using the SDRAM machine See Section 11...

Page 451: ...hine for the 60x bus and one for the local bus The machines provide the necessary control functions and signals for JEDEC compliant SDRAM devices Each bank can control a SDRAM device on the 60x or the...

Page 452: ...ATA 0 7 DATA 56 63 DATA 0 7 DATA 56 63 CS 0 7 PSDRAS PSDWE PSDCAS CS7 CS0 CS7 CS0 PSDDQM 0 7 DQM0 DQM7 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 2x1M x8 SDRAM x8 x8 x8 A 17 D 0 63 PowerQUICC II PSDA10 A 19 28 x8...

Page 453: ...ach SDRAM device 1 Issue a PRECHARGE ALL BANKS command 2 Issue eight CBR REFRESH commands NOTE If the SDRAM does not require eight CBR REFRESH COMMANDS then the SDRAM requirement should be followed 3...

Page 454: ...ency burst length and burst type is programmed into the P LSDMR register by initialization software at reset After the P LSDMR is set the PowerQUICC II transfers the information to the SDRAM array by...

Page 455: ...Bus Mode The BNKSEL signals provide the following functionality in single PowerQUICC II bus mode If bank based interleaving is used BNKSEL signals facilitate compatibility with SDRAMs that have diffe...

Page 456: ...o read write interval P LSDMR ACTTORW See Section 11 4 6 2 Activate to Read Write Interval CAS latency column address to first data out P LSDMR CL See Section 11 4 6 3 Column Address to First Data Out...

Page 457: ...es present P LSDMR BUFCMD See Section 11 4 6 8 External Address and Command Buffers BUFCMD The following sections describe the SDRAM parameters that are programmed in the P LSDMR register 11 4 6 1 Pre...

Page 458: ...y As seen in Figure 11 22 this parameter controlled by P LSDMR CL defines the timing for first read data after a column address is sampled by the SDRAM Figure 11 22 CL 2 2 Clock Cycles CLK ALE CS SDRA...

Page 459: ...CL parameter Figure 11 23 LDOTOPRE 2 2 Clock Cycles 11 4 6 5 Last Data In to Precharge Write Recovery As demonstrated in Figure 11 24 this parameter controlled by P LSDMR WRC defines the earliest tim...

Page 460: ...X should be set Setting this bit causes the memory controller to add another cycle for each address phase Figure 11 26 demonstrates the timing when EAMUX equals 1 Note that EAMUX can also be set in an...

Page 461: ...re 11 27 illustrates the timing when BUFCMD equals 1 Figure 11 27 BUFCMD 1 11 4 7 SDRAM Interface Timing Figure 11 28 through Figure 11 36 show SDRAM timing for various types of accesses Figure 11 28...

Page 462: ...Read Page Closed CL 3 Figure 11 31 SDRAM Four Beat Burst Read Page Miss CL 3 CLK ALE CS SDRAS SDCAS MA 0 11 Column WE DQM Data D0 Z CLK ALE CS SDRAS SDCAS MA 0 11 Row Column WE DQM Data D0 D1 CLK ALE...

Page 463: ...Hit Figure 11 33 SDRAM Three Beat Burst Write Page Closed Figure 11 34 SDRAM Read after Read Pipeline Page Hit CL 3 CLK ALE CS SDRAS SDCAS MA 0 11 Column WE DQM Data D0 CLK ALE CS SDRAS SDCAS MA 0 11...

Page 464: ...t size For 64 bit port size it is a burst of 4 For 32 bit port size it is a burst of 8 For reads that require less than the full burst length extraneous data in the burst is ignored For writes that re...

Page 465: ...on the specific SDRAM devices used and the operating frequency of the PowerQUICC II s bus This value should allow for a potential collision between memory accesses and refresh cycles The period of the...

Page 466: ...machines 11 4 11 SDRAM Refresh Timing The memory controller implements bank staggering for the auto refresh function This reduces instantaneous current consumption for memory refresh operations Once...

Page 467: ...select signals that are multiplexed over the address lines should be adjacent to the row address during the ACTIVATE command refer to Table 11 23 So the value of PSDMR BSMA is selected according to th...

Page 468: ...erleaving this means that the address bus should be partitioned as shown in Table 11 26 The following parameters can be extracted PSDMR PBI 0 ORx BPD 01 4 internal banks ORx ROWST 0100 row starts at A...

Page 469: ...to the device refresh requirements 11 5 General Purpose Chip Select Machine GPCM Users familiar with the MPC8xx memory controller should read Section 11 5 4 Differences between MPC8xx s GPCM and MPC8...

Page 470: ...devices can use BCTLx as read write indicators The BCTLx signals appears as R W in the timing diagrams See Section 11 2 7 Data Buffer Controls BCTLx and LWR Additional control is available in 60x com...

Page 471: ...ine at different timings with respect to the external address bus CS can be output in any of three configurations Simultaneous with the external address Table 11 31 GPCM Strobe Signal Behavior Option...

Page 472: ...d directly to CE of the memory device and BCTL0 is connected to the respective R W in the peripheral device Figure 11 41 GPCM Peripheral Device Interface Figure 11 42 shows CS as defined by the setup...

Page 473: ...ls the timing for the appropriate strobe negation in write cycles When this attribute is asserted the strobe is negated one quarter of a clock before the normal case For example when ACS 00 and CSNT 1...

Page 474: ...ided for memory systems that require more relaxed timing between signals When TRLX 1 and ACS 00 an additional cycle between the address and strobes is inserted by the PowerQUICC II memory controller S...

Page 475: ...negated one clock earlier as shown in Figure 11 48 and Figure 11 49 When a bank is selected to operate with external transfer acknowledge SETA and TRLX 1 the memory controller does not support externa...

Page 476: ...X 1 OE deasserts on the rising clock edge coinciding with or immediately after CS deassertion 11 5 1 5 Programmable Wait State Configuration The GPCM supports internal PSDVAL generation It allows fast...

Page 477: ...some combination of ORx 29 30 TRLX and EHTR Any access following a read access to the slower memory bank is delayed by the number of clock cycles specified by Table 11 32 See Figure 11 50 through Figu...

Page 478: ...cale Semiconductor Figure 11 51 GPCM Read Followed by Read ORx 29 30 01 Figure 11 52 GPCM Read Followed by Write ORx 29 30 01 Clock Address PSDVAL CSx CSy BCTLx OE Data Hold Time 1 cycle hold time all...

Page 479: ...onverted to PSDVAL which terminates the current GPCM access GTA should be asserted for one cycle Note that because GTA is synchronized bus termination may occur three cycles after GTA assertion so in...

Page 480: ...t size during system reset by using the configuration mechanism described in Section 5 4 Reset Configuration The boot chip select does not provide write protection CS0 operates this way until the firs...

Page 481: ...s on the 60x and local bus Additional control is available in 60x compatible mode 60x bus only using the external address latch enable ALE However ALE is not a UPM controlled signal it toggles with ch...

Page 482: ...cts If the UPM reads a RAM word with WAEN set the external UPMWAIT signal is sampled and synchronized by the memory controller and the current request is frozen When a new access to external memory is...

Page 483: ...in the RAM array is associated with each of these cycle type Figure 11 56 shows the start addresses of these patterns in the UPM RAM according to cycle type RUN commands MxMR OP 11 however can initia...

Page 484: ...dware associated with memory refresh timer request generation PURT defines the period for the timers associated with UPMx on the 60x bus and LURT defines it on the local bus See Section 11 3 8 60x Bus...

Page 485: ...The UPM provides a mechanism by which memory control signals can meet the timing requirements of the device without losing data The mechanism is the exception pattern that defines how the UPM deassert...

Page 486: ...change if specified in the RAM array at any positive edge of T1 T2 T3 or T4 there is a propagation delay specified in the Hardware Specifications Note however that only the CS signal corresponding to...

Page 487: ...or the corresponding output pins at the appropriate timing Figure 11 60 UPM Signals Timing Example 11 6 4 The RAM Array The RAM array for each UPM is 64 locations deep and 32 bits wide as shown in Fig...

Page 488: ...eld CST1 CST2 CST3 CST4 BST1 BST2 BST3 BST4 G0L G0H G1T1 G1T3 G2T1 G2T3 Reset R W R W Addr MCR MAD indirect addressing of 1 of 64 entries 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field G3T1 G3T...

Page 489: ...BxTx 5 BST2 Byte select timing 2 Defines the state of BS during clock phase 2 0 The value of the BS lines at the rising edge of T2 will be 0 1 The value of the BS lines at the rising edge of T2 will...

Page 490: ...line 3 timing 3 Defines the state of GPL3 during phase 3 4 0 The value of the GPL3 line at the rising edge of T3 will be 0 1 The value of the GPL3 line at the rising edge of T3 will be 1 See Section...

Page 491: ...exception pattern at the exception start address EXS at a fixed address in the RAM array When the PowerQUICC II under UPM control begins accessing a memory device the external device may assert TEA or...

Page 492: ...uest NA is reserved under other patterns 29 UTA UPM transfer acknowledge Indicates assertion of PSDVAL sampled by the bus interface in the current cycle 0 PSDVAL is not asserted in the current cycle 1...

Page 493: ...tion and the address accessed Figure 11 64 shows how UPMs control BS signals Figure 11 64 BS Signal Selection The uppermost byte select BS0 indicates that D 0 7 contains valid data during a cycle Like...

Page 494: ...s decremented by one Continued loop execution depends on the loop counter If the counter is not zero the next RAM word executed is the loop start word Otherwise the next RAM word executed is the one a...

Page 495: ...he value of the DLT3 bit in the same RAM word indicates when the data input is sampled by the internal bus master assuming that MxMR GPLx4DIS 1 If G4T4 DLT3 functions as DLT3 and DLT3 1 in the RAM wor...

Page 496: ...rd with the WAEN bit set the external UPMWAIT signal is sampled by the memory controller in the following cycle and the request is frozen The UPMWAIT signal is sampled at the rising edge of CLKIN If U...

Page 497: ...x EHTR Accesses after a read access to the slower memory bank is delayed by the number of clock cycles specified by Table 11 32 The information in Section 11 5 1 6 Extended Hold Time on Read Accesses...

Page 498: ...als are controlled only by the pattern written to the array Timing of GPL 0 5 In the MPC8xx s UPM the GPL lines could change on the positive edge of T2 or T3 In the PowerQUICC II these signals can cha...

Page 499: ...ch can serve multiple UPMs Refresh on the 60x bus must be done in UPMA on the local bus it must be done in UPMB New feature Repeated execution of the current RAM word REDO Extended hold time on reads...

Page 500: ...device used The MS field should indicate the specific UPM selected to handle the cycle The RAM array of the UPM can than be written through use of the MxMR OP 11 Figure 11 56 shows the first location...

Page 501: ...0 Bit 5 bst3 1 0 0 Bit 6 bst4 1 0 0 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3...

Page 502: ...1 0 0 Bit 6 bst4 1 0 1 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo...

Page 503: ...0 0 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo 0 Bit 22 redo 1 Bi...

Page 504: ...it 6 bst4 1 0 0 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo 0 Bit 2...

Page 505: ...6 bst4 1 0 1 0 1 0 1 0 1 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 red...

Page 506: ...0 0 Bit 5 bst3 0 0 1 Bit 6 bst4 0 0 1 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g...

Page 507: ...g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo 0 Bit 22 redo 1 Bit 23 loop 0 Bit 24 ex...

Page 508: ...mory Controller MPC8260 PowerQUICC II Family Reference Manual Rev 2 11 90 Freescale Semiconductor The timing diagram in Figure 11 75 shows how the burst read access shown in Figure 11 70 can be reduce...

Page 509: ...bst4 1 1 1 1 1 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 Bit 12 g1t3 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 DLT3 1 1 1 1 1 Bit 18 g4t3 0 0 0 0 0 Bit 19 g5t1 Bit 20...

Page 510: ...mes a CLKIN frequency of 66 MHz and that the device needs a 1 024 cycle refresh every 10 s Table 11 44 EDO Connection Field Value Example Explanation Field Value Machine select UPMA BRx MS 0b100 Port...

Page 511: ...0 PowerQUICC II Family Reference Manual Rev 2 Freescale Semiconductor 11 93 Disable timer period MxMR DSx 0b10 Burst inhibit device ORx BI 0b0 Table 11 44 EDO Connection Field Value Example continued...

Page 512: ...bst4 1 0 0 0 1 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 0 0 0 0 0 Bit 12 g1t3 0 0 0 0 1 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3...

Page 513: ...0 Bit 6 bst4 1 0 0 1 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 1 1 1 1 Bit 12 g1t3 1 1 1 1 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t...

Page 514: ...0 1 Bit 6 bst4 1 0 0 1 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 1 1 1 1 Bit 12 g1t3 1 1 1 1 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20...

Page 515: ...0 Bit 10 g0h1 Bit 11 g1t1 0 0 0 0 0 0 0 0 0 0 0 Bit 12 g1t3 0 0 0 0 0 0 0 0 0 0 1 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo 0 Bit 22 r...

Page 516: ...9 g0h0 Bit 10 g0h1 Bit 11 g1t1 1 1 1 1 1 1 1 1 1 1 Bit 12 g1t3 1 1 1 1 1 1 1 1 1 1 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g5t3 Bit 21 redo 0 Bit 22...

Page 517: ...t 6 bst4 0 1 1 1 1 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 1 1 1 1 1 Bit 12 g1t3 1 1 1 1 1 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit 20 g...

Page 518: ...Bit 4 bst2 1 Bit 5 bst3 1 Bit 6 bst4 1 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t1 1 Bit 12 g1t3 1 Bit 13 g2t1 Bit 14 g2t3 Bit 15 g3t1 Bit 16 g3t3 Bit 17 g4t1 Bit 18 g4t3 Bit 19 g5t1 Bit...

Page 519: ...s not ready The memory controller synchronized this signal because the wait signal is asynchronous As a result of the wait signal being asserted the UPM enters a freeze mode at the rising edge of CLKI...

Page 520: ...s PSDVAL should be pulled up 11 9 2 PowerQUICC II External Masters An PowerQUICC II external master is a 60x compatible master with additional functionality As described in the following it has fewer...

Page 521: ...s As soon as the external master asserts TS the memory controller compares the address with each of its defined valid banks If a match is found the memory controller asserts the address latch enable A...

Page 522: ...peration and Memory Access in 60x Compatible Mode Figure 11 85 shows the 1 cycle delay for external master access For systems that use the 60x bus with low frequency 33 MHz the 1 cycle delay for exter...

Page 523: ...11 86 shows an interconnection in which a 60x compatible external master and the PowerQUICC II can share access to a SDRAM bank Note that the address multiplexer is controlled by SDAMUX while the add...

Page 524: ...onductor Figure 11 86 External Master Configuration with SDRAM Device SDAMUX TT 0 4 A 0 31 DQM 0 7 CS1 TS TBST TA Arbitration signals D 0 63 SDRAM Multiplexer PowerQUICC II External Master Latch MA AL...

Page 525: ...but to the L2 cache which can be accessed more quickly write operation latency is reduced along with contention for the memory system In copy back mode cacheable read operations that hit in the L2 ca...

Page 526: ...ry memory write transaction In write through mode cacheable read operations that hit in the L2 cache are serviced from the L2 cache without requiring a memory transaction and its associated latency Th...

Page 527: ...py back This removes the need for the L2 cache to maintain a dirty bit in the tag RAM all cache blocks are unmodified and it also removes the need for bus arbitration signals The L2 cache is configure...

Page 528: ...rQUICC II s DP 0 7 signals are connected to the L2 cache s DP 0 7 signals The L2 s TSIZ 0 2 signals are pulled down to always indicate 8 byte transaction size The L2 s A 29 31 signals are pulled down...

Page 529: ...d must use either ECC BRx DECC 0b11 or read modify write parity BRx DECC 0b10 See Section 11 3 1 Base Registers BRx for more information about the PowerQUICC II base register parameters Only PowerQUIC...

Page 530: ...I s L2 interface The parameters should be configured as follows BCR EBM 1 PowerQUICC II in 60x compatible mode BCR L2C 1 L2 cache is present TS TT 0 4 TBST A 0 31 CI GBL TA DBB TEA CPU_BR CPU_BG CPU_D...

Page 531: ...hat the PowerQUICC II s internal space IMMR and any memory banks assigned to the local bus are always considered non cachable 12 4 L2 Cache Operation When configured for an L2 cache BCR L2C 1 the Powe...

Page 532: ...C II Family Reference Manual Rev 2 12 8 Freescale Semiconductor Figure 12 4 Read Access with L2 Cache CLK BR BG Addr TS ABB A0 TBST CI Memc controls AACK DBG DBB DATA TA D00 active A1 TBST D01 D02 D03...

Page 533: ...shift register The test logic which is implemented using static logic design is independent of the device system logic The PowerQUICC II s implementation provides the capability to do the following P...

Page 534: ...nals Signal Description TCK A test clock input to synchronize the test logic TMS A test mode select input with an internal pull up resistor that is sampled on the rising edge of TCK to sequence the TA...

Page 535: ...ry scan register has been included on the PowerQUICC II that can be connected between TDI and TDO when EXTEST or SAMPLE PRELOAD instructions are selected It is used for capturing signal pin data on th...

Page 536: ...13 3 Output Pin Cell O Pin Figure 13 4 Observe Only Input Pin Cell I Obs 1 1 MUX 1 1 MUX G1 C D C D From Last Cell Clock DR Update DR Shift DR 1 EXTEST Clamp Data from To Output Buffer 0 Otherwise Log...

Page 537: ...13 5 13 4 Instruction Register The PowerQUICC II JTAG implementation includes the public instructions EXTEST SAMPLE PRELOAD and BYPASS and also supports the CLAMP instruction One additional public ins...

Page 538: ...MPLE PRELOAD Initializes the boundary scan register output cells before the selection of EXTEST This initialization ensures that known data appears on the outputs when entering an EXTEST instruction S...

Page 539: ...d should be tied high or low to preclude mid level inputs To ensure that the scan chain test logic is kept transparent to the system logic the TAP controller is forced into the test logic reset state...

Page 540: ...IEEE 1149 1 Test Access Port MPC8260 PowerQUICC II Family Reference Manual Rev 2 13 8 Freescale Semiconductor...

Page 541: ...itialization and operation protection as well as the external system bus Chapter 16 CPM Multiplexing describes the CPM multiplexing logic CMX which connects the physical layer UTOPIA MII modem lines C...

Page 542: ...most of the common parts convergence sublayer CP CS of these protocols Chapter 31 ATM AAL1 Circuit Emulation Service describes the implementation of circuit emulation service CES using ATM adaptation...

Page 543: ...sors that implement the PowerPC architecture There are two versions one that describes the functionality of the combined 32 and 64 bit architecture models and one that describes only the 32 bit model...

Page 544: ...don t care n Indicates an undefined numerical value NOT logical operator AND logical operator OR logical operator Acronyms and Abbreviations Table i contains acronyms and abbreviations used in this do...

Page 545: ...unications Administrations C I Condition indication channel used in the GCI protocol CLP Cell loss priority CP Communications processor CP CS Common part convergence sublayer CPM Communications proces...

Page 546: ...oup JTAG Joint Test Action Group LAN Local area network LIFO Last in first out LRU Least recently used LSB Least significant byte lsb Least significant bit MAC Multiply accumulate or media access cont...

Page 547: ...t SMC Serial management controller SNA Systems network architecture SPI Serial peripheral interface SRAM Static random access memory SRTS Synchronous residual time stamp TDM Time division multiplexed...

Page 548: ...MPC8260 PowerQUICC II Family Reference Manual Rev 2 IV 8 Freescale Semiconductor...

Page 549: ...er Interfaces with the embedded G2core processor through a dual port RAM and virtual DMA channels for each peripheral controller Dual port RAM size is device specific 24 Kbyte on 0 29 m HiP3 devices a...

Page 550: ...C bus controller Time slot assigner supports multiplexing of data from any of the SCCs FCCs SMCs and MCCs onto eight time division multiplexed TDM interfaces The time slot assigner supports the follow...

Page 551: ...e set of communications capabilities A subset of the possible configurations using an PowerQUICC II is shown in Table 14 1 Baud Rate Generators 60x Bus 2 MCCs1 3 FCCs2 4 SCCs 2 SMCs SPI I2C To SIU 4 T...

Page 552: ...P is a single shared resource used by all of the CPM s communications peripherals the combined service requests from all of the communications peripherals must not exceed the CP s capacity The amount...

Page 553: ...4 3 3 CP Block Diagram The CP contains the following functional units Scheduler and sequencer Instruction decoder Execution unit Load store unit LSU Block transfer module BTM moves data between serial...

Page 554: ...ith the G2 core in several ways General Load Store Unit Block Transfer Dual Port RAM Microcode DMA Execution Source Buses Destination Bus Address Data Address Data Address Data Peripheral Bus Schedule...

Page 555: ...g effective FIFO sizes of two characters Table 14 2 shows the order in which the CP handles requests from peripherals from highest to lowest priority NOTE Emergency Prioritization Elevation to emergen...

Page 556: ...onfiguration Register RCCR The RISC controller configuration register RCCR as shown in Figure 14 3 configures the CP to run microcode from ROM or RAM and controls the CP s internal timer 16 FCC3 trans...

Page 557: ...y Controls the priority of the MCCs in relation to the other communication peripherals See Table13 2 Peripheral Prioritization for more information 0 Original CPM priority scheme MCCx priority behaves...

Page 558: ...port RAM 111 Reserved 19 29 m HiP3 devices Reserved ERAM 25 m HiP4 devices ERAM 16 19 Enable RAM microcode Configure as instructed in the download process of a Freescale supplied RAM microcode package...

Page 559: ...ode for DONE 1 2 for IDMA 1 2 See Section 19 7 2 DONEx DONE 1 2 asserts as follows 0 High to low change 1 Low to high change 29 DEM34 Edge detect mode for DONE 3 4 for IDMA 3 4 See Section 19 7 2 DONE...

Page 560: ...ed in that device Table 14 5 describes which microcode version numbers are associated with each silicon revision 14 4 Command Set The core issues commands to the CP by writing to the CP command regist...

Page 561: ...16 17 18 25 26 27 28 31 Field MCC channel number MCN OPCODE Reset 0000_0000_0000_0000 R W R W Addr 0x119C2 Figure 14 6 CP Command Register CPCR Table 14 6 CP Command Register Field Descriptions Bit Na...

Page 562: ...1000 00111 IDMA3 10110 01001 SMC2 01001 01000 IDMA4 10111 01010 RAND 01110 01010 11 14 Reserved 15 FLG Command semaphore flag Set by the core and cleared by the CP 0 The CP is ready to receive a new c...

Page 563: ...INIT TX PARAMS INIT TX PARAMS INIT TX PARAMS INIT TX PARAMS INIT TX PARAMS 0011 ENTER HUNT MODE ENTER HUNT MODE ENTER HUNT MODE INIT MCC RX AND TX PARAMS one channel 1 1 Not available on 29 m HiP3 Rev...

Page 564: ...tion 28 7 MCC Commands INIT TX PARAMS Initialize transmit parameters Initializes the transmit parameters of the peripheral controller Note that for the MCCs issuing this command initializes only 32 ch...

Page 565: ...out The GCI performs the timeout function RESET BCS Reset block check sequence Used in BISYNC mode to reset the block check sequence calculation MCC STOP TRANSMIT See Section 28 7 MCC Commands MCC ST...

Page 566: ...s the memory map of the dual port RAM NOTE Starting at address 0x4000 on 25 m HiP4 devices an extra 8 Kbytes is available for microcode execution only and cannot be used for data buffers or BDs Howeve...

Page 567: ...as they are not in the same bank Only the parameters in the parameter RAM and the microcode RAM option require fixed addresses to be used The BDs buffer data and scratchpad RAM can be located in the d...

Page 568: ...buffer mode the IDMA channel also uses BDs They are described in Section 19 3 IDMA Emulation NOTE The CPM accesses BDs by initiating a DMA cycle on either the 60x or local bus If BDs are located in DP...

Page 569: ...C2 256 7 0x8600 FCC32 2 Reserved on the MPC8255 256 8 0x8700 MCC13 3 Reserved on the MPC8250 and the MPC8255 128 0x8780 Reserved 124 0x87FC SMC1_BASE 2 0x87FE IDMA1_BASE 2 9 0x8800 MCC2 128 0x8880 Res...

Page 570: ...66 MHz Continuously updated reference counter All operations on the RISC timer tables are based on a fundamental tick of the CP s internal timer that is programmed in the RCCR The tick is a multiple o...

Page 571: ...restart bit is 1 R_TMR should not be modified by the user The SET TIMER command should be used instead 0x06 R_TMV RISC timer valid register Used exclusively by the CP to determine if a timer is curre...

Page 572: ...writing ones writing zeros does not affect bit values The RISC timer mask register RTMR is used to enable interrupts that can be generated in the RTER Setting an RTMR bit enables the corresponding in...

Page 573: ...o save space 3 Clear the TM_CNT field in the RISC timer table parameter RAM to show how many ticks elapsed since the RISC internal timer was enabled This step is optional 4 Clear RTER if it is not alr...

Page 574: ...it times out 8 Write 0x29E1_0008 to the CPCR to issue the SET TIMER command 9 Set RCCR TIME to enable the RISC timer to begin operation 14 6 8 RISC Timer Interrupt Handling The following sequence desc...

Page 575: ...ser can use this technique to push CP performance to its limit The user should use the standard initialization sequence and incorporate the following differences 1 Program the tick of the RISC timers...

Page 576: ...Communications Processor Module Overview MPC8260 PowerQUICC II Family Reference Manual Rev 2 14 28 Freescale Semiconductor...

Page 577: ...r Figure 15 1 shows a block diagram of the time slot assigner TSA Two SI blocks in the PowerQUICC II SI1 and SI2 can be programmed to handle eight TDM lines concurrently with the same flexibility desc...

Page 578: ...igner TSA R clocks T clocks R clocks T clocks R sync T sync TDM A B C D Pins Strobes Route SI RAM Tx Rx RAM Control Mode Register TDM A B C D Tx TX Command Register Status Register SMC1 SMC2 SCC1 SCC2...

Page 579: ...and receive clocks allowed Selection of rising falling clock edges for the frame sync and data bits Supports 1 and 2 input clocks 1 or 2 clocks per data bit Selectable delay 0 3 bits between frame syn...

Page 580: ...SDN channels The TDMa channel can support E3 or DS 3 rates as a clear channel in a parallel nibble interface FCC in HDLC mode clock ratio 1 6 or serial interface clock ratio 1 4 TSA programming is ind...

Page 581: ...t 1 Slot 3 SCC2 More complex TDM example unique routing SCC2 SMC1 SCC2 SCC2 SMC1 SCC2 TDM Tx TDM Rx Even more complex TDM example multiple time slot per SCC2 SMC1 SCC2 TDM Tx TDM Rx Most complex TDM e...

Page 582: ...nterfacing to other devices that do not support the multiplexed interface or for enabling disabling three state I O buffers in a multiple transmitter architecture Notice that open drain programming on...

Page 583: ...he entire TDM signal rather than just on a particular serial channel Loopback mode causes the physical interface to receive the same signal it is sending The SI loopback mode checks more than the indi...

Page 584: ...ording to the programming of the RAMs The four SIx RAM banks can be configured in many different ways to support various TDM channels The user can define the size of each SIx RAM that is related to a...

Page 585: ...5 One TDM Channel with Static Frames and Independent Rx and Tx Routes 15 4 2 One Multiplexed Channel with Dynamic Frames In the configuration shown in Figure 15 6 one multiplexed channel has 256 entr...

Page 586: ...obe outputs If MCC is set the entry refers to the corresponding MCC otherwise it refers to other serial controllers Figure 15 7 shows the entry fields for both cases The use of MCC slots is restricted...

Page 587: ...onsecutive SIx RAM entries remains continuously asserted for both entries A strobe asserted on the last entry in a table is negated after the last entry is processed Note Each strobe is changed with t...

Page 588: ...source the SWTR feature can cause erratic behavior Also note this feature does not work with nibble operation When MCC 1 the SIx RAM entry fields function as described in Table 15 2 14 BYT Byte resolu...

Page 589: ...MCC2 channel numbers Note Note that the channel programming must be coherent with the MCCF see Section 28 6 MCC Configuration Registers MCCFx 11 13 CNT Count If SUPER 0 normal mode CNT indicates the n...

Page 590: ...4 bits B2 strobe 2 4 bits B2 SMC1 1 bit D SCC1 strobe 1 Each of these six divisions can be supported by a single SIx RAM entry Thus six SIx RAM entries are needed See Table 15 3 NOTE IDL requires the...

Page 591: ...orresponding sync arrives the SI exchanges the shadow RAM with the current route RAM and resets CSRxn to indicate that the operation is complete At this time the user may change the routing again Noti...

Page 592: ...ddress CSRTa 0 CSRRb 0 CSRTb 0 CSRRa 1 CSRTa 1 CSRRb 1 CSRTb 1 CSRRa 0 CSRTa 0 CSRRb 0 CSRTb 0 L1RCLKb L1RSYNCb 64 RXb Shadow 64 RXa 64 RXb Route Route Framing Signals L1RCLKa L1RSYNCa 64 RXa Shadow R...

Page 593: ...for each TDM channel SIxAMR SIxBMR SIxCMR and SIxDMR They are used to define SI operation modes and allow the user with SIx RAM to support any or all of the ISDN channels independently when in IDL or...

Page 594: ...n the entries of SIx RAM blocks for every TDM used that is before the starting address of the next TDM 000 First bank first 32 entries 001 First bank second 32 entries 010 Second bank first 32entries...

Page 595: ...Useful when the transmit and receive sections of a given TDM use the same clock and sync signals In this mode L1TCLKx and L1TSYNCx can be used for their alternate functions 0 Separate pins The receiv...

Page 596: ...CMXSCR GRx bit is set The grant is a sample of L1GRx while L1RSYNCx is asserted This grant mechanism implies the IDL access controls for transmission on the D channel See Section 15 6 2 IDL Interface...

Page 597: ...th a 1 bit frame sync delay Figure 15 15 Falling Edge FE Effect When CE 0 and xFSD 01 Figure 15 16 shows the effects of changing FE when CE 1 with no frame sync delay L1TxD Rx Sampled Here L1ST L1SYNC...

Page 598: ...FE when CE 0 with no frame sync delay L1TXD L1ST L1SYNC L1CLK Bit 0 On Bit 0 xFSD 00 FE 0 CE 1 The L1ST is Driven from Sync Data is Driven from Clock Low L1TXD L1ST L1SYNC Bit 0 On Bit 0 FE 0 L1ST is...

Page 599: ...the starting addresses of the shadow section in the SIx RAM for each of the TDM channels L1TXD L1ST L1SYNC L1CLK Bit 0 On Bit 0 xFSD 00 FE 1 CE 0 The L1ST is Driven from Sync Data is Driven From Cloc...

Page 600: ...12 Reserved Should be cleared 1 3 5 7 9 11 13 15 SSADx Starting bank address for the shadow RAM of TDM a b c or d Defines the starting bank address of the shadow SIx RAM section that belongs to the c...

Page 601: ...M is valid The SI exchanges between the RAMs and take the new receive routing from the receiver shadow RAM Cleared as soon as the switch has completed 1 3 5 7 CSRTx Change shadow RAM for TDM a b c or...

Page 602: ...l adaptor shown in Figure 15 22 In such an application the IDL interface is used to connect the 2B D channels between the PowerQUICC II CODEC and S T transceiver One of the PowerQUICC II s SCCs is con...

Page 603: ...following the pulse designate the IDL frame L1RXDx IDL receive data input to the PowerQUICC II Valid only for the bits supported by the IDL ignored for any other signals present L1TXDx IDL transmit d...

Page 604: ...route them transparently to an SCC or SMC Use the SPI to perform out of band signaling The PowerQUICC II supports all channels of the IDL bus in the basic rate Each bit in the IDL frame can be routed...

Page 605: ...sections interface to the same IDL bus set SIxMR CRTx to internally connect the Rx clock and sync signals to the transmit section Then program the SIx RAM used for the IDL channels to the preferred r...

Page 606: ...31 Configures L1TCLKa and L1RCLKa 13 Set PPARB 17 Configures L1RQa 14 Clear PSORB 17 Configures L1RQa 15 Set PDIRB 17 Configures L1RQa 16 Set PPARD 13 Configures L1ST1 17 Clear PSORD 13 Configures L1...

Page 607: ...igure 15 24 Figure 15 24 GCI Bus Signals In addition to the 144 Kbps ISDN 2B D channels the GCI provides five channels for maintenance and control functions B1 is a 64 Kbps bearer channel B2 is a 64 K...

Page 608: ...on this bit that the channel is free If a collision is detected on the D channel the physical layer device sets bit 4 of C I channel 2 to logic high The PowerQUICC II then aborts its transmission and...

Page 609: ...nd sync signals and program the GRx bits to transfer the D channel grant to the SCC that supports this channel The received grant bit should be marked by programming the channel select bits of the SIx...

Page 610: ...PDIRA 9 Configures L1TXDa 0 9 Set PODRA 9 Configures L1TXDa 0 to an open drain output 10 Set PPARC 30 31 Configures L1TCLKa and L1RCLKa 11 Clear PDIRC 30 31 Configures L1TCLKa and L1RCLKa 12 Clear PSO...

Page 611: ...s the connection of the serial devices to the SIs for using the time slot assigner TSA This allows any combination of MCCs FCCs SCCs and SMCs to multiplex data on any of the eight TDM channels The CMX...

Page 612: ...d also to an 8 bit ATM UTOPIA level 2 interface not on the MPC8250 FCC2 can also be connected also to the TC layer MPC8264 and MPC8266 only Time Slot Assigner SIx R clocks T clocks R sync T sync TDM A...

Page 613: ...0 PHYs FCC1 connect up to 15 PHYs and FCC2 connect up to 1 PHYs FCC1 connect up to 7 PHYs and FCC2 connect up to 3 PHYs FCC1 connect up to 3 PHYs and FCC2 connect up to 7 PHYs FCC1 connect up to 1 PH...

Page 614: ...k of 8 internal BRGs and 20 external CLK pins see Figure 16 3 There are two main advantages to the bank of clocks approach First a serial device is not forced to choose a serial device clock from a pr...

Page 615: ...can be connected to any given FCC or SCC receiver or transmitter The SMC transmitter and receiver share the same clock source when connected to the NMSI Table 16 1 shows the clock source options for t...

Page 616: ...V SCC3 Rx V V V V V V V V SCC3 Tx V V V V V V V V SCC4 Rx V V V V V V V V SCC4 Tx V V V V V V V V FCC1 Rx V V V V V V V V FCC1 Tx V V V V V V V V FCC2 Rx V V V V V V V V FCC2 Tx V V V V V V V V FCC3...

Page 617: ...an internal rate feature is used This enables the user to implement a multiple PHY UTOPIA master or slave on both FCC1 and FCC2 using only twenty pins The user chooses how many PHYs to use with each i...

Page 618: ...nected to FCC2 The user decides which FCC uses the remaining two pins by programming CMXUAR MADx See Figure 16 5 8 9 F1IRB FCC1 internal rate BRG selection Selects the BRG to be connected to FCC 1 for...

Page 619: ...2 M S M S M S M S 5 5 5 5 5 5 5 5 8 5 8 5 0 1 2 3 4 4 3 2 1 0 These three bits always relate These three bits always relate to FCC2 master Pins to an FCC1 master These two address bits relate to the m...

Page 620: ...PHYs to be consecutive for each FCC that is the address lines connected to each FCC must be consecutive Figure 16 7 describes the interconnection between the receive external multi PHY bus and the int...

Page 621: ...b lsb FCC1 Rx msb lsb FCC2 Rx msb lsb FCC2 Rx msb lsb FCC1 RxAddr 4 GND GND GND GND GND GND GND GND GND GND FCC1 FCC2 PIO PIO PIO PIO PIO PIO PIO PIO FCC2 RxAddr 3 master FCC2 RxAddr 0 slave FCC1 RxAd...

Page 622: ...Register CMXSI1CR Table 16 3 CMXSI1CR Field Descriptions Bits Name Description 0 RTA1CS Receive TDM A1 clock source 0 TDM A1 receive clock is CLK1 1 TDM A1 receive clock is CLK19 1 RTB1CS Receive TDM...

Page 623: ...lock source 0 TDM A2 receive clock is CLK13 1 TDM A2 receive clock is CLK5 1 RTB2CS Receive TDM B2 clock source 0 TDM B2 receive clock is CLK15 1 TDM B2 receive clock is CLK17 2 RTC2CS Receive TDM C2...

Page 624: ...pins versus FCCn pins is made in the parallel I O control register 1 FCC1 is connected to the TSA of the SIs The NMSIx pins are available for other purposes 2 4 RF1CS Receive FCC1 clock source NMSI m...

Page 625: ...nsmit FCC2 clock source NMSI mode Ignored if FCC2 is connected to the TSA FC2 01 000 FCC2 transmit clock is BRG5 001 FCC2 transmit clock is BRG6 010 FCC2 transmit clock is BRG7 011 FCC2 transmit clock...

Page 626: ...ared 0 1 2 4 5 7 8 9 10 12 13 15 Field GR1 SC1 RS1CS TS1CS GR2 SC2 RS2CS TS2CS Reset 0000_0000_0000_0000 R W R W Addr 0x0x11B08 16 17 18 20 21 23 24 25 26 28 29 31 Field GR3 SC3 RS3CS TS3CS GR4 SC4 RS...

Page 627: ...to the TSA and is either connected directly to the NMSIx pins or is not used The choice of general purpose I O port pins versus SCCn pins is made in the parallel I O control register 1 SCC2 is connec...

Page 628: ...3 TS3CS Transmit SCC3 clock source NMSI mode Ignored if SCC3 is connected to the TSA SC3 1 000 SCC3 transmit clock is BRG1 001 SCC3 transmit clock is BRG2 010 SCC3 transmit clock is BRG3 011 SCC3 tran...

Page 629: ...mode Ignored if SCC4 is connected to the TSA SC4 1 000 SCC4 transmit clock is BRG1 001 SCC4 transmit clock is BRG2 010 SCC4 transmit clock is BRG3 011 SCC4 transmit clock is BRG4 100 SCC4 transmit cl...

Page 630: ...and is either connected directly to the NMSIx pins or is not used The choice of general purpose I O port pins versus SMCn pins is made in the parallel I O control register 1 SMC2 is connected to the T...

Page 631: ...equencies Each BRG contains an autobaud support option Each BRG output can be routed to a pin BRGOn Figure 17 1 shows a BRG Figure 17 1 Baud Rate Generator BRG Block Diagram Each BRG clock source can...

Page 632: ...the output of the BRG can be sent to the autobaud control block 17 1 BRG Configuration Registers 1 8 BRGCx The BRG configuration registers BRGCx are shown in Figure 17 2 A reset disables the BRG and...

Page 633: ...RG input clock comes from the CLK5 pin If BRG3 4 7 8 The BRG input clock comes from the CLK15 pin 11 Reserved 18 ATB Autobaud Selects autobaud operation of the BRG on the corresponding RXD ATB must re...

Page 634: ...nterrupt handler can then adjust BRGCx CD DIV16 see Table 17 3 for accuracy before the first character is fully received ensuring that the UART recognizes all characters After a full character is rece...

Page 635: ...cal bit rates of asynchronous communication Note that here the internal clock rate is assumed to be 16 the baud rate that is GSMRx_L TDCR GSMRx_L RDCR 0b10 For synchronous communication the internal c...

Page 636: ...BRGs MPC8260 PowerQUICC II Family Reference Manual Rev 2 17 6 Freescale Semiconductor For example to get a rate of 64 kbps the system clock can be 24 96 MHz BRGCx DIV16 0 and BRGCx CD 389 BRGCx EXTC B...

Page 637: ...grammed by the user Figure 18 1 shows the timer block diagram Figure 18 1 Timer Block Diagram Pin assignments for TINx TGATEx and TOUTx are described in Section 40 5 Ports Tables 18 1 Features The key...

Page 638: ...o 256 and the output of the prescaler is used as an input to the 16 bit counter The best resolution of the timer is one clock cycle 16 ns at 66 MHz The maximum period when the reference value is all o...

Page 639: ...e internal clock 18 2 1 Cascaded Mode In this mode two 16 bit timers can be internally cascaded to form a 32 bit counter Timer 1 may be internally cascaded to timer 2 and timer 3 can be internally cas...

Page 640: ...set timer 0 Reset the corresponding timer a software reset is identical to an external reset 1 Enable the corresponding timer if the STP bit is cleared 4 GM1 Gate mode for TGATE1 This bit is valid onl...

Page 641: ...clocks to the timer remain stopped until the user clears this bit or a hardware reset occurs 3 RST4 Reset timer 0 Reset the corresponding timer a software reset is identical to an external reset 1 Ena...

Page 642: ...pt on capture event 11 Capture on any TINx edge and enable interrupt on capture event 10 OM Output mode 0 Active low pulse on TOUTx for one timer input clock cycle as defined by the ICLK bits Thus TOU...

Page 643: ...s not running Use TRRx to define the preferred count value 18 2 7 Timer Event Registers TER1 TER4 Each timer event register TERx shown in Figure 18 9 reports events recognized by the timers When an ou...

Page 644: ...CAP Reset 0x0000 Addr 0x0x10DB0 TER1 0x0x10DB2 TER2 0x0x10DB4 TER3 0x0x10DB6 TER4 Figure 18 9 Timer Event Registers TER1 TER4 Table 18 4 TER Field Descriptions Bits Name Description 0 13 Reserved sho...

Page 645: ...A IDMA channels Figure 19 1 shows data flow paths Data from the peripheral controllers can be routed to external RAM using the 60x bus path 1 or the local bus path 2 Figure 19 1 SDMA Data Paths On a p...

Page 646: ...channel can arbitrate for the bus against the other internal devices and any external devices present Once an SDMA channel becomes system bus master it remains bus master for one transaction which can...

Page 647: ...es SDSR fields 0 5 6 7 Field SBER_L SBER_P Reset 0000_0000 Addr 0x0x11018 Figure 19 3 SDMA Status Register SDSR Table 19 1 SDSR Field Descriptions Bits Name Description 0 5 Reserved should be cleared...

Page 648: ...x10058 19 2 4 SDMA Transfer Error MSNUM Registers PDTEM and LDTEM There are two SDMA transfer error MSNUM registers PDTEM and LDTEM MSNUM 0 4 contains the sub block code SBC used to identify the curre...

Page 649: ...e IDMA can be programmed in the IDMA parameter RAM to achieve maximum system performance The IDMA supports two buffer handling modes auto buffer and buffer chaining The auto buffer mode allows blocks...

Page 650: ...single accesses until alignment is achieved Then burst transactions are used if allowed by the user to transfer the bulk of the data buffer Single accesses are used again for any remaining non bursta...

Page 651: ...red A remainder of 0 31 bytes is left in the transfer buffer after the last burst write Last phase The remaining data is read into the transfer buffer in bursts with the last 1 31 bytes read in single...

Page 652: ...s SS_MAX every DREQ assertion causes one transfer to the smaller in STS DTS terms bus If STS DTS asserting DREQ triggers one read transfer automatically followed by one write transfer NOTE External re...

Page 653: ...t size transfers The transfer sizes STS DTS related to the peripheral must be programmed to its port size thus every access to a peripheral yields a single bus transaction The maximum peripheral port...

Page 654: ...ripheral will most likely assert DONE before overflowing the buffer When DONE is asserted the BD is closed and interrupts are generated if enabled The next DREQ assertion opens the next BD if DCM DT i...

Page 655: ...DACK The constant assertion of DACK enables the controller to read from memory as soon as the peripheral samples the data bus Thus data is transferred from memory to a peripheral in one data phase ins...

Page 656: ...is the solution for moderately loaded bus as the dual port RAM buffer is emptied in 7 DMA write transfers of nine bursts each before the next long PCI DMA read The IDMA transfer size parameters give...

Page 657: ...O ports To enable the IDMA signals the corresponding bits in the parallel I O registers should be set See Chapter 40 Parallel I O Ports 19 7 1 DREQx and DACKx When the peripheral requires IDMA servic...

Page 658: ...e mode the IDMA requests service by the CPM whenever its DREQ signal is active This is true regardless of whether or not an IDMA is in progress Therefore whenever the IDMA s DREQ is active all CPM per...

Page 659: ...he device the IDMA asserts DACK The device must use TA and TEA for data validation Thus DACK is the acknowledgment of the original transaction request given on DREQx 19 7 2 DONEx This bidirectional op...

Page 660: ...I O Registers The core initiates the IDMA BDs to point to the data for the transfer and or a free space for data to be transferred to and starts the transfer by issuing the START_IDMA command During d...

Page 661: ...mmand is issued 19 8 2 IDMAx Parameter RAM When an IDMAx channel is configured to auto buffer or buffer chaining mode the PowerQUICC II uses the IDMAx parameters listed in the Table 19 4 Parameters sh...

Page 662: ...quantity of data inside the internal buffer 0x0A SS_MAX Hword Steady state maximum transfer size in bytes User defined parameter to increase microcode efficiency Initialize to internal_buffer_size 32...

Page 663: ...or peripherals In fly by mode DTS is initialized to the peripheral port size In memory to memory mode DTS value is initialized to SS_MAX STS value is initialized to SS_MAX DTS can be initialized to va...

Page 664: ...er whenever DMA_WRAP bytes have been transferred to from the buffer 000 64 byte 001 128 byte 010 256 byte 011 512 byte 100 1024 byte 101 2048 byte 11x Reserved Table 19 7 and Table 19 8 describes the...

Page 665: ...ee Table 19 6 00 Read from memory write to memory 10 Read from peripheral write to memory 01 Read from memory write to peripheral 11 Reserved When a device is a peripheral DACK is asserted during tran...

Page 666: ...y while asserting DACK to peripheral Peripheral samples the data read from memory On the bus singles or bursts depends on DTS 10 1 Peripheral to memory STS port size or 32 Write transaction to memory...

Page 667: ...Bytes DTS in Bytes 000 64 1 32 01 1 32 1 2 4 8 single 1 32 burst 2 1 These values come out as a single transaction on the bus 2Peripherals that can accept bursts of 32 bytes are supported 10 1 2 4 8 s...

Page 668: ...fields 19 8 5 IDMA BDs Source addresses destination addresses and byte counts are presented to the CP using the special IDMA BDs The CP reads the BDs programs the SDMA channel and notifies the core a...

Page 669: ...is serviced this bit is cleared by CP unless CM 1 1 Reserved should be cleared 2 W Wrap final BD in table 0 This is not the last BD in the BD table 1 Last BD in the table After the associated buffer h...

Page 670: ...e 0 DONE is inactive during this BD 1 The IDMA asserts DONE at the last read data phase of the BD In fly by mode DCM FB 1 SDN should be same as DDN 10 DDN Destination done 0 DONE is inactive during th...

Page 671: ...s set and an interrupt is generated to the core if enabled STOP_IDMA command was issued The channel has finished a transfer of a BD with the last bit L set If the START_IDMA command is reissued and ch...

Page 672: ...performed 19 10 IDMA Bus Exceptions Bus exceptions can occur while the IDMA has the bus and is transferring operands In any computer system a hardware failure can cause an error during a bus transact...

Page 673: ...ch port is controlled by five I O registers PPAR PSOR PDIR PODR and PDAT Each bit in these registers controls the external pin of the same location PPARC selects the pins general purpose 0 dedicated 1...

Page 674: ...in PPARA PDIRA PODRA PSORA Default IDMA3 DREQ3 I PA 0 1 0 0 1 GND DACK3 O PA 2 1 1 0 1 DONE3 I O PA 1 1 0 1 1 VDD IDMA4 DREQ4 I PA 5 1 0 0 1 GND DACK4 O PA 3 1 1 0 1 DONE4 I O PA 4 1 0 1 1 VDD Table 1...

Page 675: ...edge low to high DONE is high to low Request priority is higher than the SCCs 88FE 0x0300 IDMA2_BASE points to 0x0300 where the parameter table base address is located for IDMA2 CPCR 0x22A1_0009 STAR...

Page 676: ...ransferred DCM S D 01 Memory to peripheral mode DONE DREQ and DACK are connected to the peripheral DCM SINC 1 The memory address is incremented after every transfer DCM DINC 1 The memory address is in...

Page 677: ...mented constantly Last transaction of the last BD is combined with DONE assertion Another DREQ assertion after last BD complete will issue IDSR OB interrupt to the core STOP_IDMA BD is closed SC bit i...

Page 678: ...egister is programmed to enable all interrupts SIMR_L 0x00000800 Interrupt controller is programmed to enable interrupts from IDMA1 RCCR 0x00200000 IDMA1 configuration Internal request priority is the...

Page 679: ...scribed in Chapter 25 SCC Ethernet Mode Although the selected protocol usually applies both to the SCC transmitter and receiver one half of an SCC can run transparent operations while the other runs a...

Page 680: ...se L Clocks can be derived from a baud rate generator an external pin or DPLL Data rate for asynchronous communication can be as high as 16 62 Mbps at 133 MHz Supports automatic control of the RTS CTS...

Page 681: ...GSMR2 0x11A46 GSMR3 0x11A66 GSMR4 Figure 20 2 GSMR_H General SCC Mode Register High Order Table 20 1 GSMR_H Field Descriptions Bit Name Description 0 15 Reserved should be cleared 16 17 TCRC Transpare...

Page 682: ...on while the Rx Tx clock is low at which time the transfer begins Useful for connecting PowerQUICC II in transparent mode since the RTS of one PowerQUICC II can connect directly to the CD CTS of anoth...

Page 683: ...s on a 16 bit sync pattern stored in the DSR 30 RTSM RTS mode Determines whether flags or idles are to be sent Can be changed on the fly 0 Send idles between frames as defined by the protocol and the...

Page 684: ...ime for the external transceiver 4 5 TSNC Transmit sense Determines the amount of time the internal carrier sense signal stays active after the last transition on RXD indicating that the line is free...

Page 685: ...idles are sent 14 15 TDCR Transmitter receiver DPLL clock rate If the DPLL is not used choose 1 mode except in asynchronous UART mode where 8 16 or 32 must be chosen TDCR should match RDCR in most ap...

Page 686: ...data if CD is asserted CTS is ignored 11 Loopback and echo mode Loopback and echo operation occur simultaneously CD and CTS are ignored See the loopback bit description above for clocking requirement...

Page 687: ...me synchronization The programmed value for DSR depends on the protocol UART DSR is used to configure fractional stop bit transmission BISYNC and transparent DSR should be programmed with the sync pat...

Page 688: ...hat can reside anywhere in dual port RAM The total number of 8 byte BDs is limited only by the size of the dual port RAM 128 BDs 1 Kbyte These BDs are shared among all serial controllers SCCs SMCs SPI...

Page 689: ...r pointer points to the beginning of the buffer in memory internal or external For an RxBD the value must be a multiple of four word aligned For a TxBD this pointer can be even or odd Shown in Figure...

Page 690: ...using a TxBD which keeps it from being retransmitted before it is confirmed by the core However some protocols support a continuous mode CM for which R is not cleared always ready The CPM uses RxBDs...

Page 691: ...Map for All Protocols Offset 1 Name Width Description 0x00 RBASE Hword Rx TxBD table base address offset from the beginning of dual port RAM The BD tables can be placed in any unused portion of the du...

Page 692: ...al byte count is a down count value initialized with MRBLR and decremented with each byte written by the supporting SDMA channel 0x14 Word Rx temp3 0x18 TSTATE Word Tx internal state3 0x1C Word Tx int...

Page 693: ...ld GBL BO TC2 DTB Reset 0000_0000_0000_0000 R W R W Addr SCCx base 0x04 RFCRx SCCx base 0x05 TFCRx Figure 20 8 Function Code Registers RFCR and TFCR Table 20 6 RFCRx TFCRx Field Descriptions Bits Name...

Page 694: ...more than one RxBD A common practice is to process all RxBDs in the interrupt handler until one is found with RxBD E set 4 Execute the rfi instruction Table 20 7 SCCx Event Mask and Status Registers...

Page 695: ...enable interrupts 11 Set GSMR_L ENT and GSMR_L ENR Descriptors can have their R or E bits set at any time Notice that the CPCR does not need to be accessed after a hardwarereset An SCC should be disa...

Page 696: ...pe data negating it during frame transmission causes a CTS lost error Negating CTS forces RTS high and Tx data to become idle If GSMR_H CTSS is zero the SCC must sample CTS before a CTS lost is recogn...

Page 697: ...ampled on the rising Rx clock edge before data is received If GSMR_H CDS is 1 CD transitions cause data to be immediately gated into the receiver 1 GSMR_H CTSS 0 CTSP 0 or no CTS lost can occur TCLK T...

Page 698: ...racter In addition the UART protocol has an option for CTS flow control as described in Chapter 21 SCC UART Mode If CTS is already asserted when RTS is asserted transmission begins in two additional b...

Page 699: ...he DPLL can be bypassed by selecting 1x mode for GSMR_L RDCR TDCR If the DPLL is bypassed only NRZ or NRZI encodings are available The DPLL must not be used when an SCC is programmed to Ethernet and i...

Page 700: ...data stream for transitions when one is detected the DPLL adjusts the count to produce an output clock that tracks incoming bits The DPLL has a carrier sense signal that indicates when data transfers...

Page 701: ...PLL is used to recover the clock in the 8 16 or 32 modes Synchronization occurs internally after the DPLL generates the Rx clock Therefore even the fastest DPLL clock generation the 8 option easily me...

Page 702: ...ter and put it in reset state 3 Modify SCC Tx parameters or parameter RAM To switch protocols or restore the initial Tx parameters issue an INIT TX PARAMETERS command Table 20 9 DPLL Codings Coding De...

Page 703: ...switch protocols or restore Rx parameters to their initial state issue an INIT RX PARAMETERS command 3 If the INIT RX PARAMETERS command was not issued in step 2 issue an ENTER HUNT MODE command 4 Se...

Page 704: ...Serial Communications Controllers SCCs MPC8260 PowerQUICC II Family Reference Manual Rev 2 20 26 Freescale Semiconductor...

Page 705: ...s is sent idle condition Because the start bit is always a zero the receiver can detect when real data is once again on the line UART specifies an all zeros break character which ends a character tran...

Page 706: ...gnal and address bit It also supports synchronous operation where a clock internal or external must be provided with each bit received 21 1 Features The following list summarizes main features of an S...

Page 707: ...ipped by the SCC A parity bit can be generated in transmission and checked during reception although it is not stored in the buffer its value can be inferred from the buffer s reporting mechanism Simi...

Page 708: ...CP PAREC counts received parity errors FRMEC counts received characters with framing errors NOSEC counts received characters with noise errors BRKEC counts break conditions on the signal A break condi...

Page 709: ...e See Section 21 9 Receiving Control Characters 21 6 Error and Status Reporting Overrun parity noise and framing errors are reported via the BDs and or error counters in the UART parameter RAM Signal...

Page 710: ...once transmission stops then the UART Tx parameters including the TxBD can be modified TBPTR points to the next TxBD in the table Transmission begins once the R bit of the next BD is set and a RESTAR...

Page 711: ...ined in a control character table in the UART parameter RAM Each incoming character is compared to the table entries using a mask the received control character mask RCCM to strip don t cares If a mat...

Page 712: ...gh SCCE CCR The current Rx buffer is not closed 2 7 Reserved 8 15 CHARACTERn Control character values 1 8 Defines control characters to be compared to the incoming character For characters smaller tha...

Page 713: ...ransmission The TOSEQ character in CHARSEND is sent at a higher priority than the other characters in the transmit buffer but does not preempt characters already in the transmit FIFO This means that t...

Page 714: ...BD P is set the SCC sends a preamble sequence idle character before sending the buffer For example for 8 data bits no parity 1 stop bit and 1 start bit a preamble of 10 ones is sent before the first c...

Page 715: ...tted stop bit 31 32 0000 Last transmitted stop bit 17 32 For 8 oversampling 1111 Last transmitted stop bit 8 8 Default value after reset 1110 Last transmitted stop bit 7 8 1101 Last transmitted stop b...

Page 716: ...ally but increments the noise error counter NOSEC Note that this error does not occur in synchronous mode Idle Sequence Receive If the UART is receiving data and gets an idle character all ones the ch...

Page 717: ...and are ignored when the character is sent CL can be modified on the fly 00 5 data bits 01 6 data bits 10 7 data bits 11 8 data bits 4 5 UM UART mode Selects the asynchronous channel protocol UM can b...

Page 718: ...ous UART operation GSMR_L TENC RENC must select NRZ and GSMR_L RDCR TDCR select 1 mode A bit is transferred with each clock and is synchronous to the clock which can be internal or external 9 DRT Disa...

Page 719: ...scale Semiconductor 21 15 An ENTER HUNT MODE or CLOSE RXBD command is issued An address character is received in multidrop mode The address character is written to the next buffer for a software compa...

Page 720: ...Rx BD 2 Status Length Pointer 1 XXXX 32 Bit Buffer Pointer E Rx BD 3 Status Length Pointer Byte 1 Byte 2 Byte 8 Buffer Byte 9 Byte 10 Buffer Byte 1 Byte 2 Byte 3 Buffer Byte 4 Error Empty Additional B...

Page 721: ...led by the CPM indicating the need for the core to process the buffer Setting SCCE RX causes an interrupt if not masked 4 C Control character 0 This buffer does not contain a control character 1 The l...

Page 722: ...during reception 15 CD Carrier detect lost Set when the carrier detect signal is negated during reception 0 1 2 3 4 5 6 7 8 9 15 Offset 0 R W I CR A CM P NS CT Offset 2 Data Length Offset 4 Tx Buffer...

Page 723: ...secutive buffers 5 A Address Valid only in multidrop mode automatic or manual 0 This buffer contains only data 1 This buffer contains address characters All data in this buffer is sent as address char...

Page 724: ...nd Mask Register SCCM CD IDL RX CCR IDL RX IDL BRKS BRKE IDL CD Break Line Idle 10 Characters RXD CD Characters Received by UART Time Line Idle TXD RTS Characters Transmitted by UART CTS TX CTS CTS Li...

Page 725: ...d Multiple BRKS events are not received if a long break sequence is received 11 Reserved should be cleared Refer to note 1 below 12 CCR Control character received and rejected Set when a control chara...

Page 726: ...start of dual port RAM followed by one TxBD write RBASE with 0x0000 and TBASE with 0x0008 7 Write 0x04A1_0000 to CPCR to execute the INIT RX AND TX PARAMS command for SCC2 This command updates RBPTR a...

Page 727: ...buffer is closed after 16 bytes are received Data received after 16 bytes causes a busy out of buffers condition because only one RxBD is prepared 21 22 S Records Loader Application This section descr...

Page 728: ...ontrol characters XOFF E should be cleared R should be set Whenever the core receives a control character received CCR interrupt and the RCCR contains XOFF the software should immediately stop transmi...

Page 729: ...e protocols permit addressing beyond 16 bits The 8 or 16 bit control field provides a flow control number and defines the frame type control or data The exact use and structure of this field depends o...

Page 730: ...ars TxBD R buffer ready At the end of the current buffer if TxBD L is not set multiple buffers per frame only TxBD R is cleared Before the SCC proceeds to the next TxBD in the table an interrupt can b...

Page 731: ...ames The received frames threshold parameter RFTHR can be used to postpone interrupts until a specified number of frames is received This function can be combined with a timer to implement a timeout i...

Page 732: ...nt RFTHR 0x4E HMASK Hword Mask register HMASK and four address registers HADDRn for address recognition The SCC reads the frame address from the HDLC receiver compares it with the HADDRs and masks the...

Page 733: ...his GRACEFUL STOP TRANSMIT Stops transmission smoothly Unlike a STOP TRANSMIT command it stops transmission after the current frame is finished or immediately if no frame is being sent SCCE GRA is set...

Page 734: ...rrun occurs during a frame whose address is not recognized an RxBD with data length two is opened to report the overrun and the interrupt is generated CD Lost during Frame Reception Highest priority e...

Page 735: ...nable 0 No retransmission 1 Automatic frame retransmission is enabled Particularly useful in the HDLC bus protocol and ISDN applications where multiple HDLC controllers can collide Note that retransmi...

Page 736: ...lost CTS may not be reported on the buffer frame it occurred on This can improve performance of HDLC transmissions of small back to back frames or when the number of flags between frames should be lim...

Page 737: ...L error Set when a DPLL error occurs while this buffer is being received DE is also set due to a missing transition when using decoding modes in which a transition is required for every bit Note that...

Page 738: ...ter Address 1 Address 2 Control Byte Buffer CRC Byte 1 CRC Byte 2 Buffer Address 1 Address 2 Buffer Control Byte Empty 8 Bytes 8 Bytes 8 Bytes 8 Bytes Two Frames Received in HDLC Unexpected Abort Stor...

Page 739: ...BDs in this table is determined by TxBD W and the space constraints of the dual port RAM 3 I Interrupt 0 No interrupt is generated after this buffer is processed 1 SCCE TXB or SCCE TXE is set when thi...

Page 740: ...e 22 7 HDLC Event Register SCCE HDLC Mask Register SCCM Table 22 9 SCCE SCCM Field Descriptions 1 Bits Name Description 0 4 Reserved should be cleared Refer to note 1 below 5 DCC DPLL carrier sense ch...

Page 741: ...me Description CD IDL FLG RXB RXF IDL CD Line Idle Stored in Rx Buffer RXD CD Frame Received by HDLC Time Line Idle TXD RTS Frame Transmitted by HDLC CTS TXB CTS CTS Line Idle Line Idle Stored in Tx B...

Page 742: ...26 PPARC 12 13 and PDIRD 26 and clear PDIRC 12 13 PSORC 12 13 and PSORD 26 0 4 5 6 7 Field FG CS ID Reset 0000_0000 R W R Addr 0x0x11A17 SCCS1 0x0x11A37 SCCS2 0x0x11A57 SCCS3 0x0x11A77 SCCS4 Figure 2...

Page 743: ...ITT CRC 12 Write C_PRES with 0x0000FFFF to comply with 16 bit CCITT CRC 13 Clear DISFC CRCEC ABTSC NMARC and RETRC for clarity 14 Write MFLR with 0x0100 so the maximum frame size is 256 bytes 15 Write...

Page 744: ...ter and receiver This additional write to GSMR_L2 ensures that ENT and ENR are enabled last 22 15 HDLC Bus Mode with Collision Detection The HDLC controller includes an option for hardware collision d...

Page 745: ...on for short distance configurations rather than the more complex S T interface Any HDLC based frame protocol can be used at layer 2 not just LAPD HDLC bus devices wait 8 10 rather than 7 10 bit times...

Page 746: ...HDLC controller features Automatic HDLC bus access Automatic retransmission in case of collision May be used with the NMSI or a TDM bus Delayed RTS mode 22 15 2 Accessing the HDLC Bus The HDLC bus pro...

Page 747: ...address and source address are included in the HDLC frame then a predefined priority of stations results if two stations begin to transmit simultaneously they necessarily detect a collision no later t...

Page 748: ...irst bit Setting PSMR BRM delays RTS by one bit which is useful when the HDLC bus connects multiple local stations to a transmission line If the transmission line driver has a one bit delay the delaye...

Page 749: ...r L1TXDx and L1RXDx Because collisions are still detected from the individual SCC CTS pin it must be configured to connect to the chosen SCC Because the SCC only receives clocks during its time slot C...

Page 750: ...o 1 Set BRM to 1 if delayed RTS is desired Configure CRC to 16 bit CRC CCITT 0b00 Configure other bits to zero or default To program the general SCC mode register GSMR set the bits as described below...

Page 751: ...n a frame A DLE sent as data must be preceded by a DLE character This is sometimes called byte stuffing The physical layer of the BISYNC communications link must synchronize the receiver and transmitt...

Page 752: ...ter a buffer is sent if the last TxBD L and the Tx block check sequence TxBD TB bits are set the BISYNC controller appends the CRC16 LRC and then writes the message status bits in TxBD status and cont...

Page 753: ...ncoming data exceeds the buffer length the controller fetches the next BD if E is zero reception continues to its buffer When a BCS is received it is checked and written to the buffer The BISYNC contr...

Page 754: ...s are issued to the CP command register CPCR Transmit commands are described in Table 23 2 0x40 BDLE Hword BISYNC DLE register Contains the value to be sent as the first byte of a DLE SYNC pair and st...

Page 755: ...Ds can be modified The TBPTR points to the next TxBD Transmission resumes when the R bit of the next BD is set and a RESTART TRANSMIT is issued RESTART TRANSMIT Lets characters be sent on the transmit...

Page 756: ...ample the end of text character ETX implies an end of block ETB with a subsequent BCS An enquiry ENQ character designates an end of block without a subsequent BCS All the control characters are writte...

Page 757: ...he buffer is closed 0 The character is written into the receive buffer and the buffer is closed 1 The character is written into the receive buffer The receiver waits for one LRC or two CRC bytes of BC...

Page 758: ...r and includes it in the BCS If it is not a DLE or SYNC the controller examines the control character table and acts accordingly If the character is not in the table the buffer is closed with the DLE...

Page 759: ...pins Table 23 8 describes transmit errors Table 23 6 BDLE Field Descriptions Bits Name Description 0 V Valid If V 1 and the receiver is not in hunt mode when a SYNC character is received this charact...

Page 760: ...yte over the previously received byte The previous character and its status bits are lost The channel then closes the buffer sets RxBD OV and generates the RXB interrupt if it is enabled Finally the r...

Page 761: ...on of a received byte to determine whether it should used in BCS calculation 0 Disable receive BCS 1 Enable receive BCS Should be set or reset within the time taken to receive the following data byte...

Page 762: ...parity If the parity bit is not low a parity error is reported 10 Even parity An even number must result from the calculation performed at both ends of the line 11 High parity If the parity bit is no...

Page 763: ...CS 6 CM Continuous mode 0 Normal operation 1 The CP does not clear E after this BD is closed the buffer is overwritten when the CP accesses this BD next However E is cleared if an error occurs during...

Page 764: ...be cleared 2 W Wrap last BD in table 0 Not the last BD in the table 1 Last BD in the table After this buffer is used the CP sends data using the BD pointed to by TBASE The number of TxBDs in this tabl...

Page 765: ...r which saves writing the first DLE to a separate buffer in transparent mode See TR for information on control characters 9 TR Transparent mode 0 The transmitter enters and stays in normal mode after...

Page 766: ...rrier sense status generated by the DPLL changes Real time status can be found in SCCS This is not the CD status discussed elsewhere Valid only when DPLL is used 6 7 Reserved should be cleared Refer t...

Page 767: ...r analyzing the initial characters of a block either set PSMR RTR or issue a RESET BCS CALCULATION command For example if a DLE STX is received enter transparent mode By setting the appropriate PSMR b...

Page 768: ...3 and PSORD 26 3 Configure port C pin 29 to enable the CLK3 pin Set PPARC 29 and clear PDIRC 29 and PSORC 29 4 Connect CLK3 to SCC2 using the CPM mux Write 0b110 to CMXSCR R2CS and CMXSCR T2CS 5 Conne...

Page 769: ...00 to the SIU interrupt mask register low SIMR_L so the SMC1 can generate a system interrupt Initialize SIU interrupt pending register low SIPNR_L by writing 0xFFFF_FFFF to it 24 Write 0x0000002C to G...

Page 770: ...SCC BISYNC Mode MPC8260 PowerQUICC II Family Reference Manual Rev 2 23 20 Freescale Semiconductor...

Page 771: ...h Transparent mode is configured in the GSMR see Section 20 1 1 The General SCC Mode Registers GSMR1 GSMR4 Transparent mode is selected in GSMR_H TTX TRX for the transmitter and receiver respectively...

Page 772: ...e number of bytes can be sent If GSMR_H REVD is set the bit order of each byte is reversed before being sent the msb of each octet is sent first Setting GSMR_H TFL makes the transmit FIFO smaller and...

Page 773: ...register DSR see Section 20 1 3 Data Synchronization Register DSR Pattern length is specified in GSMR_H SYNL as shown in Table 24 1 See also Section 20 1 1 The General SCC Mode Registers GSMR1 GSMR4...

Page 774: ...erQUICC II A and PowerQUICC II B exchange transparent frames and synchronize each other using RTS and CD However CTS is not required because transmission begins at any time Thus RTS is connected direc...

Page 775: ...ack testing through the TDM expect to receive several bytes of 0xFF before the actual data 24 4 2 1 Inline Synchronization Pattern The receiver can be programmed to begin receiving data into the recei...

Page 776: ...nt For the 16 bit CRC CCITT initialize with 0x0000_FFFF For the 32 bit CRC CCITT initialize with 0xFFFF_FFFF and for the CRC 16 initialize with ones 0x0000_FFFF or zeros 0x0000_0000 0x 34 CRC_ C Long...

Page 777: ...in the table ENTER HUNT MODE forces the transparent receiver to the current frame and enter hunt mode where the transparent controller waits for the synchronization sequence After receiving the comma...

Page 778: ...ve buffer descriptor Table 24 7 describes RxBD status and control fields Table 24 6 Receive Errors Error Description Overrun The SCC maintains a receive FIFO The CPM starts programming the SDMA channe...

Page 779: ...V CD DE are set Note that the SCC transparent controller writes the number of buffer not frame octets to the last BD s data length field 0 Not the last buffer in a frame 1 Last buffer in a frame 5 F F...

Page 780: ...is not ready for transmission The BD and buffer can be updated The CPM clears R after the buffer is sent or after an error is encountered 1 The user prepared buffer is not sent yet or is being sent Th...

Page 781: ...bes SCCE SCCM fields 6 CM Continuous mode 0 Normal operation 1 The CPM does not clear TxBD R after this BD is closed so the buffer is automatically resent when the CPM accesses this BD next However Tx...

Page 782: ...d Refer to note 1 below 13 BSY Busy condition Set when a byte or word is received and discarded due to a lack of buffers The receiver resumes reception after it gets an ENTER HUNT MODE command 14 TXB...

Page 783: ...ith 0x10 for normal operation 10 Write MRBLR with the maximum number of bytes per receive buffer and assume 16 bytes so MRBLR 0x0010 11 Write CRC_P with 0x0000_FFFF to comply with the 16 bit CRC CCITT...

Page 784: ...ce Manual Rev 2 24 14 Freescale Semiconductor NOTE After 5 bytes are sent the Tx buffer is closed and after 16 bytes are received the Rx buffer is closed Any data received after 16 bytes causes a busy...

Page 785: ...erent from any type fields used in Ethernet This limits the length of the data portion of the frame to 1 500 bytes and total frame length to 1 518 bytes The last 4 bytes of the frame are the frame che...

Page 786: ...of frame or end of frame Note that the CPM of the PowerQUICC II requires a minimum system clock frequency of 24 MHz to support Ethernet 25 2 Features The following list summarizes the main features of...

Page 787: ...al 64 bin group address hash table plus broadcast address checking Promiscuous Receives all addresses but discards frame if REJECT is asserted External content addressable memory CAM support on serial...

Page 788: ...The carrier sense signal is referenced in Ethernet descriptions because it indicates when the LAN is in use Carrier sense is defined as the logical OR of RENA and CLSN Figure 25 3 shows the basic comp...

Page 789: ...case of a collision This improves bus usage and latency when the backoff timer output requires an immediate retransmission If a collision occurs during frame transmission the controller returns to th...

Page 790: ...detected during the frame the RxBDs associated with this frame are reused Thus there will be no collision frames presented to you except late collisions which indicate serious LAN problems When the d...

Page 791: ...intains these 32 bit modulo 232 counters that can be initialized while the channel is disabled CRCEC is incremented for each received frame with a CRC error not including frames not addressed to the c...

Page 792: ...received 0x50 MAXD2 Hword 0x52 MAXD Hword Rx max DMA 0x54 DMA_CNT Hword Rx DMA counter A temporary down counter used to track frame length 0x56 MAX_B Hword Maximum BD byte count 0x58 GADDR1 Hword Grou...

Page 793: ...rea 0 next frame 0x84 TBUF1_DATA1 Word Save area 1 next frame 0x88 TBUF1_RBA0 Word 0x8C TBUF1_CRC Word 0x90 TBUF1_BCNT Hword 0x92 TX_LEN Hword Tx frame length counter 0x94 IADDR1 Hword Individual addr...

Page 794: ...TX and RX PARAMETERS resets both transmit and receive parameters Table 25 3 Receive Commands Command Description ENTER HUNT MODE After hardware or software is reset and the channel is enabled in GSMR...

Page 795: ...e with the user programmed physical address in PADDR1 Address recognition can be performed on multiple individual addresses using the IADDR1 4 hash table Figure 25 4 Ethernet Address Recognition Flowc...

Page 796: ...the group individual hash table the frame is accepted Otherwise it is rejected So if eight group addresses are stored in the hash table and random group addresses are received the hash table prevents...

Page 797: ...k operation the Ethernet controller listens for data being received from the EEST at the same time that it is sending 25 15 Full Duplex Ethernet Support To run full duplex Ethernet select loopback and...

Page 798: ...nternal FIFO for receiving data When it overruns the channel writes the received byte over the previously received byte The previous byte and frame status are lost The channel closes the buffer sets R...

Page 799: ...Ethernet specifications 32 bit CCITT CRC X32 X26 X23 X22 X16 X12 X11 X10 X8 X7 X5 X4 X2 X1 1 6 PRO Promiscuous 0 Check the destination address of incoming frames 1 Receive the frame regardless of its...

Page 800: ...Data Buffer Pointer Offset 6 Figure 25 6 SCC Ethernet RxBD Table 25 7 SCC Ethernet RxBD Status and Control Field Descriptions Bits Name Description 0 E Empty 0 The buffer is full or stopped receiving...

Page 801: ...accepted in promiscuous mode but are flagged as a miss by internal address recognition Thus in promiscuous mode M determines whether a frame is destined for this station 0 The frame is received becaus...

Page 802: ...fer Pointer 1 E F Receive BD 0 Status Length Pointer 0 0x0045 32 Bit Buffer Pointer 0 E F Receive BD 1 Status Length Pointer 1 XXXX 32 Bit Buffer Pointer E Receive BD 2 Status Length Pointer 1 XXXX 32...

Page 803: ...straints of the dual port RAM Note The TxBD table must contain more than one BD in Ethernet mode 3 I Interrupt 0 No interrupt is generated after this buffer is serviced 1 SCCE TXB or SCCE TXE is set a...

Page 804: ...equired The controller writes this field after it successfully sends the buffer 14 UN Underrun Set when the Ethernet controller encounters a transmitter underrun while sending the buffer The Ethernet...

Page 805: ...red in Rx Buffer RXD RENA Frame Received in Ethernet Time Line Idle TXD TENA Frame Transmitted by Ethernet CLSN TXB GRA TXB Line Idle Line Idle Stored in Tx Buffer NOTES Ethernet SCCE Events 1 RXB eve...

Page 806: ...ND TX PARAMETERS command for this channel 8 Clear CRCEC ALEC and DISFC for clarity 9 Write PAD with 0x8888 for the PAD value 10 Write RET_LIM with 0x000F 11 Write MFLR with 0x05EE to make the maximum...

Page 807: ...T to receive the PowerQUICC II transmit data TPL and TPP are set for Ethernet requirements The DPLL is not used with Ethernet Note that the ENT and ENR are not enabled yet 26 Write 0xD555 to the DSR 2...

Page 808: ...SCC Ethernet Mode MPC8260 PowerQUICC II Family Reference Manual Rev 2 25 24 Freescale Semiconductor...

Page 809: ...y two bit times or more of line idle with no particular maximum time specified The idle time allows LocalTalk equipment to sense a carrier by detecting a missing clock on the line The remainder of the...

Page 810: ...Q frames In addition to the frame fields LocalTalk requires that the frame be FM0 differential Manchester space encoded which requires one level transition on every bit boundary If the value to be enc...

Page 811: ...ram the GSMR as described below 1 Set MODE to 0b0010 AppleTalk 2 Set DIAG to 0b00 for normal operation with CD and CTS grounded or configured for parallel I O This causes CD and CTS to be internally a...

Page 812: ...PSMR Follow these steps to program the protocol specific mode register 1 Set NOF to 0b0001 giving two flags before frames one opening flag plus one additional flag 2 Set CRC 16 bit CRC CCITT 3 Set DR...

Page 813: ...or directly to its own set of signals The receive and transmit clocks are derived from the TDM channel the internal baud rate generators or from an external 1 clock The transparent protocol allows the...

Page 814: ...I using transparent protocol can use SMSYN for synchronization to determine when to start a transfer SMSYN is not used when the SMC is in UART mode 27 1 Features The following is a list of the SMC s m...

Page 815: ...one stop bit and disable parity For a 13 bit data length with parity enabled set SL to one stop bit Writing values 0 to 3 to CLEN causes erratic behavior Character length transparent The values 3 15 s...

Page 816: ...0 Normal mode This should be selected if the character length is not larger than 8 bits 1 Transmit lower address byte first Reserved should be cleared GCI 7 PM Parity mode UART 0 Odd parity 1 Even pa...

Page 817: ...5 The SMC in GCI Mode 27 2 3 SMC Parameter RAM The CP accesses each SMC s parameter table using a user programmed pointer SMCx_BASE located in the parameter RAM see Section 14 5 2 Parameter RAM Each...

Page 818: ...ich the change occurs change MRBLR only while the SMC receiver is disabled MRBLR should be greater than zero and should be even if character length exceeds 8 bits 0x08 RSTATE Word Rx internal state 2...

Page 819: ...ter is calculated as follows 1 data length 5 to 14 1 if parity bit is used number of stop bits 1 or 2 For example for 8 data bits no parity and 1 stop bit character length is 10 bits 0x2A IDLC Hword T...

Page 820: ...7 Field GBL BO TC2 DTB R W R W Addr SMC base 0x04 RFCR SMC base 0x05 TFCR Figure 27 4 SMC Function Code Registers RFCR TFCR Table 27 3 RFCR TFCR Field Descriptions Bit Name Description 0 1 Reserved sh...

Page 821: ...ializes transmit parameters to the state they had after reset 1 Clear SMCMR TEN 2 Issue an INIT TX PARAMETERS command and make any additional changes 3 Set SMCMR TEN 27 2 4 3 SMC Receiver Full Sequenc...

Page 822: ...ion 27 3 SMC in UART Mode SMCs generally offer less functionality and performance in UART mode than do SCCs which makes them more suitable for simpler debug monitor ports instead of full featured UART...

Page 823: ...BD is not ready the SMC starts sending idles and waits for the next TxBD to be ready By appropriately setting the I bit in each BD interrupts can be generated after each buffer a specific buffer or ea...

Page 824: ...The SMC sends a programmable Table 27 4 Transmit Commands Command Description STOP TRANSMIT Disables transmission of characters on the transmit channel If the SMC UART controller receives this command...

Page 825: ...Table 27 6 SMC UART Errors Error Description Overrun The SMC maintains a two character length FIFO for receiving data Data is moved to the buffer after the first character is received into the FIFO i...

Page 826: ...ned only by the W bit and overall space constraints of the dual port RAM 3 I Interrupt 0 No interrupt is generated after this buffer is filled 1 The SMCE RXB is set when this buffer is completely fill...

Page 827: ...rnal or external memory Figure 27 7 shows the UART RxBD process showing RxBDs after they receive 10 characters an idle period and five characters one with a framing error The example assumes that MRBL...

Page 828: ...atus Length Pointer 1 XXXX 32 Bit Buffer Pointer E Receive BD 3 Status Length Pointer Byte 1 Byte 2 Byte 8 Buffer Byte 9 Byte 10 Buffer Byte 1 Byte 2 Byte 3 Buffer Byte 4 Error Empty Additional Bytes...

Page 829: ...ld Descriptions Bits Name Description 0 R Ready 0 The buffer is not ready for transmission BD and its buffer can be altered The CP clears R after the buffer has been sent or an error occurs 1 The buff...

Page 830: ...al interrupt request Figure 27 9 represents the SMCE SMCM registers Table 27 9 describes SMCE SMCM fields Figure 27 10 shows an example of the timing of various events in the SMCE 0 1 2 3 4 5 6 7 Fiel...

Page 831: ...y one TxBD write RBASE with 0x0000 and TBASE with 0x0008 6 Write 0x1D01_0000 to CPCR to execute the INIT RX AND TX PARAMETERS command 7 Write RFCR and TFCR with 0x10 for normal operation 8 Write MRBLR...

Page 832: ...are enabled last After 5 bytes are sent the TxBD is closed The receive buffer closes after receiving 16 bytes Subsequent data causes a busy out of buffers condition since only one RxBD is ready 27 4 S...

Page 833: ...rs the R bit It then starts transmitting idles When the end of the current BD is reached and the L bit is not set only R is cleared In both cases an interrupt is issued according to the I bit in the B...

Page 834: ...is is the first bit of data received The receiver does not lose synchronization again regardless of the state of SMSYN until REN is cleared Once SMCMR TEN is set the first rising edge of SMCLK that fi...

Page 835: ...iver transmitter after the frame sync indication rather than the falling edge of SMSYN Chapter 15 Serial Interface with Time Slot Assigner describes how to configure time slots The TSA allows the SMC...

Page 836: ...and to slot 2 if CLSN is 16 If a buffer has its SMC enabled then the first byte in the next buffer can appear in any time slot associated with this channel If a buffer is ended with the L bit set the...

Page 837: ...command is issued RESTART TRANSMIT Starts or resumes transmission from the current TBPTR in the channel TxBD table When the channel receives this command it polls the R bit in this BD The SMC expects...

Page 838: ...s received into the FIFO If a FIFO overrun occurs the SMC writes the received data character over the previously received character The previous character and its status bits are lost Then the channel...

Page 839: ...Normal operation 1 The CP does not clear E after this BD is closed allowing the buffer to be overwritten when the CP next accesses this BD However E is cleared if an error occurs during reception rega...

Page 840: ...writing 0 has no effect Unmasked bits must be cleared before the CP clears the internal interrupt request The SMCE and SMCM registers are displayed in Figure 27 14 2 W Wrap final BD in table 0 Not the...

Page 841: ...008 6 Write 0x1D01_0000 to CPCR to execute the INIT RX AND TX PARAMETERS command 7 Write RFCR and TFCR with 0x10 for normal operation 0 1 2 3 4 5 6 7 Field TXE BSY TXB RXB Reset 0 R W R W Addr 0x0x11A...

Page 842: ...bytes causes a busy out of buffers condition since only one RxBD is prepared 27 5 The SMC in GCI Mode The SMC can control the C I and monitor channels of the GCI frame When using the SCIT configuratio...

Page 843: ...trol bits according to the GCI monitor channel protocol When the CP stores a received data byte in the SMC RxBD a maskable interrupt is generated A TRANSMIT ABORT REQUEST command causes the PowerQUICC...

Page 844: ...BD and a maskable interrupt is generated If the SMC is configured to support SCIT channel 1 the double last look method is not used 27 5 4 SMC GCI Commands The commands in Table 27 18 are issued to th...

Page 845: ...ledges the previous byte 3 MS Data mismatch Valid only for monitor channel protocol Set when two different consecutive bytes are received cleared when the last two consecutive bytes match The SMC wait...

Page 846: ...on 0 E Empty 0 Cleared by the CP to indicate that the byte associated with this BD is available to the core 1 The core sets E to indicate that the byte associated with this BD has been read Note that...

Page 847: ...6 SMCE1 0x0x11A96 SMCE2 0x0x11A8A SMCM1 0x0x11A9A SMCM2 Figure 27 19 SMC GCI Event Register SMCE Mask Register SMCM Table 27 23 SMCE SMCM Field Descriptions Bits Name Description 0 3 Reserved should b...

Page 848: ...Serial Management Controllers SMCs MPC8260 PowerQUICC II Family Reference Manual Rev 2 27 36 Freescale Semiconductor...

Page 849: ...can be programmed to perform in a mode separate from the other channels of that MCC Proper programming of the SI and SIRAM is responsible for the routing of timeslots within a TDM stream to the approp...

Page 850: ...tion There is also one set of channel specific parameters and channel extra parameters per MCC channel containing protocol state information for that channel and pointers to that particular channel s...

Page 851: ...he BD tables associated with one MCC must reside in a 512 KByte segment The absolute base addresses of a channel BD table is MCCBASE 8 RBASE for the receiver and MCCBASE 8 TBASE for the transmitter MC...

Page 852: ...n any of this MCC s receive channels Therefore software should look for frames in all active buffer descriptor rings This parameter does not need to be reset after an interrupt 0x0A GRFCNT Hword Globa...

Page 853: ...nnel This option is programmable For each HDLC channel one of two CRC CCITT can be selected through the CHAMR 0x30 RINTTMP0 Word RINTTMPx Temporary location for holding a receive circular interrupt ci...

Page 854: ...before first frame of data Note Used in conjunction with ZISTATE and ZIDATA0 0x10 TBDFlags Hword TxDB flags used by the CP read only for the user 0x12 TBDCNT Hword Tx internal byte count Number of rem...

Page 855: ...to be everything between flags including CRC No more data is written into the current buffer when the MFLR violation is detected 0x3A MAX_CNT Hword Max_length counter used by the CP read only for the...

Page 856: ...8 4 For a descriptions of CHAMR in transparent and SS7 modes refer to Section 28 3 2 3 and Section 28 3 4 1 respectively For channels that are used in conjunction with CES functionality the user shoul...

Page 857: ...he transmitter starts sending the data of the frame If the transmission is between frames and the frame buffers are not ready the transmitter sends flags until it can start transmitting the data 1 At...

Page 858: ...er 3 13 15 NOF Number of flags NOF defines the minimum number of flags before frames 000 At least 1 flag 001 At least 2 flags 111 At least 8 flags 0 1 2 3 4 5 6 7 Field GBL BO TC2 DTB BDB Reset R W R...

Page 859: ...ed in Section 28 3 1 1 Internal Transmitter State TSTATE HDLC Mode 0x04 ZISTATE Word Zero insertion machine state User initialized to 0x10000207 for regular channel and 0x30000207 for inverted channel...

Page 860: ...el used by the CP read only for the user 0x38 TMRBLR Hword Transparent maximum receive buffer length Defines the maximum number of bytes written to a receiver buffer before moving to the next buffer f...

Page 861: ...l the TxBDs 0 Polling is disabled The CPM does not access the external bus to check the R bit in the TxBD 1 Polling is enabled POL is used to optimize the use of the external bus Software should alway...

Page 862: ...on began or can be data that was on the line previous to the arrival of the intended data 01 Slot Slot The first data is sent received in the slot defined in the slot assignment table for super channe...

Page 863: ...CHAMR AAL1 CES Figure 28 6 shows the user initialized channel mode register CHAMR for CES operation It is the same as the CHAMR in transparent mode with three extra CES fields in bits 13 15 Table 28...

Page 864: ...he new BD or multiple BDs and set BD R before enabling polling 2 3 0b11 Must be set 4 EP Empty polarity and enable polling 0 The E bit in the RxBD is handled in positive logic 1 empty 0 not empty Poll...

Page 865: ...tatus signal unit FISU LSSU filtering Octet counting Signal unit error rate monitoring Good frame counter and bad frame counting Initial alignment supports alignment error rate monitoring Host softwar...

Page 866: ...programmable delay applies to JT Q 703 standard Automatic transmission of fill in signal units FISU Automatic retransmission of signal units for link status signal unit LSSU retransmission Automatic...

Page 867: ...x7E7E7E7E allows transmission of flags before first frame of data Note Used in conjunction with ZISTATE and ZIDATA0 0x10 TBDFlags Hword TxBD flags used by the CP read only for the user 0x12 TBDCNT Hwo...

Page 868: ...when receive buffers are available JTTDelay Applies to Japanese SS7 only FISU retransmission delay specified in units of 512 s According to the Japanese SS7 standard the delay should be 24 ms and thu...

Page 869: ...rwise should be cleared Used by the CP to implement the 24 ms delay for signal unit error rate monitoring in Japanese SS7 0x78 JTRDelay Hword FISU transmit delay specified in units of 512us Applies to...

Page 870: ...Interrupt mask bits These bits are used for enabling disabling the reporting of each possible event defined in the interrupt circular table entry See Section 28 8 1 1 Interrupt Circular Table Entry 0...

Page 871: ...ter sends flags until it can start transmitting the data received for SS7 operation 1 At least one idle pattern is sent between adjacent frames The NOF value shall be no smaller than the PAD setting s...

Page 872: ...ue T Threshold 285 D Upcount 16 JTRDelay Length of interval 24ms 0x2F 0 3 4 5 6 7 8 9 10 11 12 15 Field AERM SUERM_DIS STD SF_DIS SU_FIL SEN_FIS O_ORN O_ITUT FISU_PAD Reset R W R W Figure 28 10 SS7 Co...

Page 873: ...ation of the JT Q703 error counter and ensure that an SUERM interrupt is generated on the first SU received in error After proving period set the parameters T and D to values according to the Japanese...

Page 874: ...S7 Mode To reduce the overhead to the user software a filtering algorithm has been adopted to allow superfluous frames to be discarded This algorithm compares the first 3 5 bytes depending on the type...

Page 875: ...el will remain in state 2 and SU error monitor will be adjusted accordingly If the frames do not match the current SU will be received into a buffer descriptor and the channel will return to State 0 2...

Page 876: ...both the Japanese standard and OCM features are selected 28 4 Channel Extra Parameters In addition to the information kept in the channel specific parameter ram a channel also has a set of pointers u...

Page 877: ...uperchannel may still be used as part of the superchannel Although a timeslot for a normal MCC channel may be of any length up to 8 bits a superchannelled timeslot must always be 8 bits Although a nor...

Page 878: ...rst timeslot that appears in the SIRAM programming for a transparent superchannel be the first to send or receive when the superchannel first starts The user indicates which timeslot in a superchannel...

Page 879: ...t byte condition instead Figure 28 15 shows the SI RAM programming for transparent receiver superchannels which uses the slot synchronization This example assumes a timeslot configuration similar to t...

Page 880: ...erchannel reception begins on Thus slot synchronization is not necessary and the timeslots do not need to be programmed as superchannelled timeslots and the CNT and BYT fields may be programed normall...

Page 881: ...Group 4 Reset 0000_0000 R W R W Addr 0x0x11B38 MCCF1 0x0x11B58 MCCF2 Figure 28 17 SI MCC Configuration Register MCCF Table 28 15 MCCF Field Descriptions Bits Name Description 0 1 2 3 4 5 6 7 GROUP x G...

Page 882: ...ction 28 3 1 4 Internal Receiver State RSTATE HDLC Mode and Section 28 3 1 1 Internal Transmitter State TSTATE HDLC Mode The following commands used to stop and initialize channels are issued to the M...

Page 883: ...e appropriate channel numbers The INIT TX AND RX command may be used to initialize both the receive and transmit sides of an MCC channel at the same time Note that this command will initialize the fir...

Page 884: ...annel reporting that event Each channel has an INTMSK field that determines which events on that particular channel trigger the creation of a new entry in the interrupt tables Whenever a new entry is...

Page 885: ...set 0000_0000_0000_0000 R W R W Addr 0x0x11B30 MCCE1 0x0x11B50 MCCE2 0x0x11B34 MCCM1 0x0x11B54 MCCM2 Figure 28 19 MCC Event Register MCCE Mask Register MCCM Table 28 18 MCCE MCCM Register Field Descri...

Page 886: ...After clearing it the user reads the next entry from the transmit interrupt circular table and starts processing a specific channel s exception The user returns from the interrupt handler when it reac...

Page 887: ...on 28 3 4 3 SS7 Configuration Register SS7 Mode SLIPE Only used in conjunction with AAL1 CES Slip End Set when an MCC channel interworking with an ATM channel exits the slip state the connection s CES...

Page 888: ...the TDM clock may be interpreted as an overwhelming number of clocks that the SI may try to process amongst other anomalous behavior thus draining the MCC FIFOs on that TDM much too quickly This resul...

Page 889: ...ramming errors such as incorrect values in the SIRAM entries etc 28 8 1 2 4 MCC Initialization CPCR commands for the MCC such as Init Tx Parameters and Init Rx Parameters must be issued to cover all M...

Page 890: ...up the possibility of the FCC starving out the MCC if the FCC continues to be overutilized This can lead to a GUN To help alleviate this situation setting FPSMR TPRI prevents the FCC s TX from going i...

Page 891: ...BDs chain The RxBDs chain must include at least two BDs the TxBD chain must include at least one BDs The MCC BDs are located in the external memory 28 9 1 Receive Buffer Descriptor RxBD Figure 28 21...

Page 892: ...th field 0 This buffer is not the last in a frame 1 This buffer is the last in a frame 5 F First in frame The HDLC controller sets F 1 for the first buffer in a frame In transparent mode F indicates t...

Page 893: ...ny type of nonalignment regardless of frame length The shortest frame that can be detected is of type FLAG BIT FLAG which causes the buffer to be closed with NO error indicated The following shows how...

Page 894: ...SSU retransmission Note This bit is reserved in all other modes of operation 2 W Wrap final BD in table 0 This is not the last BD in the TxBD table 1 This is the last BD in the TxBD table After this b...

Page 895: ...defined bit that the CPM never sets nor clears The user determines how this bit is used 9 10 Reserved should be cleared 11 Reserved should be cleared SUD SS7 mode only Signal unit delay 0 This buffer...

Page 896: ...FOs that are to be used are initialized 10 Enable TDM or if TDM is already enabled the user may now reprogram the TDM to include MCC related timeslots 11 If the user did not program a channel s TSTATE...

Page 897: ...al memory 6 Enable the MCC channel s as described in Section 28 3 1 1 Internal Transmitter State TSTATE HDLC Mode and Section 28 3 1 4 Internal Receiver State RSTATE HDLC Mode Under the following rest...

Page 898: ...CPM attention and possibly have to transfer data to from the memory simultaneously When MCC FIFO activity starts the MCC begins to consume CPM bandwidth immediately upon enabling a TDM which has MCC...

Page 899: ...er transmitter while HDLC SDLC protocol executes on the other half transmitter receiver Echo and local loopback modes for testing Assuming a 100 MHz CPM clock the FCCs support the following Full 10 10...

Page 900: ...data structures across all protocols the reader s learning time decreases dramatically after understanding the first protocol Each FCC supports a number of protocols Ethernet HDLC SDLC ATM and totally...

Page 901: ...rite registers cleared at reset Figure 29 2 shows the GFMR format Table 29 1 Internal Clocks to CPM Clock Frequency Ratio Mode Internal Clock CPM clock frequency ratio HDLC 1 bit 1 4 Transparent 1 bit...

Page 902: ...e but separate CLKx pins can be used if connected to the same external clock source If external loopback is preferred program DIAG for normal operation and externally connect TXD and RXD Then physical...

Page 903: ...duplex totally transparent operation for an FCC is obtained by setting both TTX and TRX Attempting to operate an FCC with Ethernet or ATM on its receiver and transparent operation on its transmitter c...

Page 904: ...error Note If SYNL 1x CDP should be cleared not in CD pulse mode 18 RTSM RTS mode 0 Send idles between frames as defined by the protocol RTS is negated between frames default 1 Send flags syncs betwee...

Page 905: ...and reenable an FCC Note that the FCC provides other tools for controlling reception the ENTER HUNT MODE command CLOSE RXBD command and RxBD E 27 ENT Enable transmit Enables the transmitter hardware s...

Page 906: ...ation as shown in the following equations The user however can request that the CP begin processing the new frame buffer without waiting the normal polling time For immediate processing after setting...

Page 907: ...ikewise receive BDs form an RxBD table The user can program the start address of the BD tables anywhere in system memory See Figure 29 5 0 1 15 Field TOD Reset 0000_0000_0000_0000 R W R W Addr 0x0x113...

Page 908: ...rs of a single frame are currently linked to the BD table It does assume however that unlinked buffers are provided by the core soon enough to be sent or received Failure to do so causes an error cond...

Page 909: ...henever the CP needs to begin using a BD because new data is arriving it checks the E bit of that BD This check is made on a prefetched copy of the current BD If the current BD is not empty it reports...

Page 910: ...but it never exceeds the MRBLR value Therefore user supplied buffers should be at least as large as the MRBLR Note that FCC transmit buffers can have varying lengths by programming TxBD Data Length a...

Page 911: ...ls 0x24 TDPTR Word TxBD data pointer Updated by the SDMA channels to show the next address in the buffer to be accessed 0x28 RBPTR Word RxBD pointer Points to the next BD that the receiver transfers d...

Page 912: ...5 FCRx Field Descriptions Bits Name Description 0 Reserved should be cleared 1 FCCP FCC priority Used in conjunction with PPC_ACR PRKM see section 4 3 2 2 and LCL_ACR PRKM see section 4 3 2 4 for a lo...

Page 913: ...D line It does not show the status of CTS and CD their real time status is available in the appropriate parallel I O port see Chapter 40 Parallel I O Ports 29 9 FCC Initialization The FCCs require a n...

Page 914: ...s long the FCC may have received more than one receive buffer Thus it is important to check more than just one RxBD during interrupt handling Typically all RxBDs in the interrupt handler are processed...

Page 915: ...ready or if it is the most recent BD marked as ready by the CPU transmit software This is to avoid an endless loop in case the CPU software fills the BD ring completely 2 A For skipping BDs manually...

Page 916: ...during frame transmission or a CTS lost error occurs The negation of CTS forces RTS high and the transmit data to the idle state If GFMR CTSS 0 the FCC must sample CTS before a CTS lost is recognized...

Page 917: ...on the rising receive clock edge before data is received If GFMR CDS 1 CD transitions immediately cause data to be gated into the receiver 1 GFMR CTSS 0 CTSP 0 or no CTS lost can occur TCLK TXD First...

Page 918: ...amically If the register or bit description states that dynamic changes are allowed the following sequences are not required and the register or bit may be changed immediately In all other cases the s...

Page 919: ...T Transmission begins using the TxBD that the TBPTR points to as soon as TxBD R 1 29 12 2 FCC Transmitter Shortcut Sequence A shorter sequence is possible if the user prefers to reinitialize the trans...

Page 920: ...at the FCC is executing HDLC without resetting the board or affecting any other FCC by taking the following steps 1 Clear GFMR ENT and GFMR ENR 2 Issue the INIT TX AND RX PARAMETERS command This comma...

Page 921: ...eal time ATM channels such as CBR and real time VBR over non real time ATM channels such as VBR ABR and UBR The ATM controller performs the ATM Forum UNI 4 0 ABR flow control To perform feedback rate...

Page 922: ...efficient memory allocation with early packet discard EPD support Interrupt report per channel using four priority interrupt queues Compliant with ATMF UNI 4 0 and ITU specification AAL5 cell format R...

Page 923: ...cell from memory CRC10 insertion option AAL1 circuit emulation service refer to Chapter 31 ATM AAL1 Circuit Emulation Service for more information AAL2 format Refer to Chapter 32 ATM AAL2 Support for...

Page 924: ...ransmission and reception CRC 10 generation check Performance monitoring support Support up to 64 bidirectional block tests simultaneously Automatic FMC and BRC cell generation and termination User tr...

Page 925: ...when no buffer is ready to transmit In this case a new ATM TRANSMIT command is needed for transmission of the VC to resume 30 2 1 1 AAL5 Transmitter Overview The transmitter reads 48 bytes from the e...

Page 926: ...total transmission rate is determined by the PHY transmission rate The FCC sends cells to keep the PHY FIFOs full the FCC inserts idle unassign cells to maintain the transmission rate Internal rate m...

Page 927: ...eption only after the last cell of the discarded AAL5 frame arrives 30 2 2 2 AAL1 Receiver Overview The ATM controller supports both AAL1 structured and unstructured formats For the unstructured forma...

Page 928: ...ng is enabled the ATM controller automatically generates and terminates FMCs forward monitoring cells and BRCs backward reporting cells See Section 30 6 6 Performance Monitoring 30 2 4 ABR Flow Contro...

Page 929: ...cation and size of each priority level s scheduling table Each scheduling table is divided into time slots as shown in Figure 30 1 The user determines the number of ATM cells to be sent each time slot...

Page 930: ...is rescheduled to the next slot For example if the line rate is 155 52 Mbps and there are eight cells per slot equation A yields a maximum VC rate of 19 44 Mbps Note that a channel can appear only on...

Page 931: ...at is generated per VC by writing to TCT ATT ATM traffic type see Section 30 10 2 3 Transmit Connection Table TCT 30 3 5 1 Peak Cell Rate Traffic Type When the peak cell rate traffic type is selected...

Page 932: ...each SCR time allotment elapses with no TxBD ready to send the APC grants the VC a credit for bursting at the peak cell rate PCR Gaining credit implies that the buffer at the switch is not full and c...

Page 933: ...drops below MDA the APC again schedules channels according to the PCR Note that in order to guarantee a minimum cell rate for UBR channels there must be enough bandwidth to simultaneously send all pos...

Page 934: ...16 bit channel code and a match status bit The external CAM fields are described in Table 30 2 0 3 4 15 16 31 PHY Addr MPHY GFC VPI VCI Figure 30 3 External CAM Data Input Fields 0 1 15 16 31 MS Chan...

Page 935: ...one of the VC level tables VCOFFSET Note that the VP table should reside in the dual port RAM In the VC level translation the VCI is compressed with the VC_MASK to generate a pointer to the VC level...

Page 936: ...he general formula for determining VCOFFSET Table 30 4 shows example VCOFFSET calculations for a VP level table with four entries Table 30 3 Field Descriptions for Address Compression Field Descriptio...

Page 937: ...e table is 4 Kbytes The address of an entry in this table is VCT_BASE VCOFFSET 4 VCpointer 4 The PowerQUICC II can check that all unallocated VCI bits are 0 by setting GMODE CUAB check unallocated bit...

Page 938: ...he channel code associated with the current OAM cell The following are optionally removed from the regular flow and sent to the raw cell queue Segment F5 OAM PTI 0b100 To enable F5 segment filtering s...

Page 939: ...ased flow control Explicit forward congestion indication EFCI The network supplies binary indication of whether congestion occurred along the connection path This information is carried in the PTI fie...

Page 940: ...vior The PowerQUICC II s implementation of ABR flow control for end system sources is described in the following steps 1 An ABR channel s allowed cell rate ACR lies between the minimum cell rate MCR a...

Page 941: ...e RM cells In this case data cells will not be sent 10 An RM cell with an incorrect CRC10 is discarded and the UNI statistics tables are updated 30 5 1 2 ABR Flow Control Destination End System Behavi...

Page 942: ...l Rev 2 30 22 Freescale Semiconductor Figure 30 11 ABR Transmit Flow Start Channel Tx ACR TCR Send RM DIR forward CCR ACR ER PCR CI NI 0 CLP 1 Schedule Time_to_send now 1 TCR ACR is low sent only EXIT...

Page 943: ...en RM Cells before a rate Decrease is required Time ADTF ACR ICR ACR is too high Idle adjust use it or loose it Unack Crm ACR ACR ACR CDF ACR max ACR MCR Unack Number of F RM cells sent without any B...

Page 944: ...B RM DATA In Rate Cell Tx B RM In Rate Cell Tx Turn around and First turn or not data in queue CI TA CI TA CI VC Send RM cell DIR backwards CCR TA ER TA MCR TA CI TA NI TA CLP 0 CI VC 0 Turn around f...

Page 945: ...RM cell supported by the PowerQUICC II For more information see the ABR flow control traffic management specification TM 4 0 on the ATM Forum website B RM Cells Rx CI 1 ACR ACR ACR RDF NI 0 ACR ACR RI...

Page 946: ...TM cell header RM VCC PTI 6 ID 6 All Protocol ID 1 DIR 7 0 Direction of RM cell 0 forward 1 backward BN 7 1 Backward notification BN 0 the cell was generated by the source BN 1 the cell was generated...

Page 947: ...f two 6 Finally send the ATM TRANSMIT command to restart channel transmission 30 6 OAM Support This section describes the PowerQUICC II s support for ATM layer F4 out of band and F5 in band operations...

Page 948: ...to this flow can be removed only by VC endpoints Segment identified by PTI 4 This flow is used for communicating operations information with the bound of one VCC link or multiple interconnected VCC li...

Page 949: ...FMC it adds the statistics generated locally across the same block to produce a backward reporting cell BRC which is then returned to the opposite endpoint The PowerQUICC II can run up to 64 bidirecti...

Page 950: ...done by the receiver After initialization see Section 30 6 6 1 whenever a cell is received for a VCC or VPC the TRCC counters are incremented and the BEDC is calculated When an FMC is received the CP...

Page 951: ...II time stamp timer see Section 14 3 8 RISC Time Stamp Control Register RTSCR The TUCs are free running counters modulo 65 536 that count transmitted user cells The total transmitted cells of a parti...

Page 952: ...own in Figure 30 19 the extra header size can vary between 1 to 12 bytes byte resolution and the HEC octet is optional For AAL5 and AAL1 CES the extra header is taken from the Rx and Tx BDs The transm...

Page 953: ...r The ATM controller processes the ATM data Possible interworking applications include the following Circuit emulation service CES Carrying voice over ATM Multiplexing several low speed services such...

Page 954: ...ic areas of the receive connection table see Section 30 10 2 2 Receive Connection Table RCT For the MCC receiver set CHAMR EP see Section 28 3 2 3 Channel Mode Register CHAMR Transparent Mode 30 9 2 U...

Page 955: ...and the SI any TDM time slot combination can be routed to a specific data buffer See Chapter 28 Multi Channel Controllers MCCs and Chapter 15 Serial Interface with Time Slot Assigner The same data buf...

Page 956: ...r without core intervention The ATM receiver and transmitter should be programed to process the same BD table When the ATM receiver fills an AAL0 buffer the ATM transmitter sends it The ATM receiver a...

Page 957: ...ET UEAD Mode Only If RCT BO 01 UEAD_OFFSET should be in little endian format For example if the UEAD entry is the first half word of the extra header in external memory UEAD_OFFSET should be programme...

Page 958: ...fined offset from dual port RAM base See Section 30 10 6 AAL1 Sequence Number SN Protection Table 0x9A Hword Reserved should be cleared 0x9C SRTS_BASE Word External SRTS logic base address AAL1 CES on...

Page 959: ...m cell rate MCR should be at least TCR 0xB2 ABR_RX_TCTE Hword ABR only Points to total of 16 bytes reserved dual port RAM area used by the CP Should be 16 byte aligned User defined offset from dual po...

Page 960: ...operation When the receive FIFO is full the ATM transmitter stops sending data cells until the receiver emergency state is cleared FIFO not full The transmitter pace is maintained although a small CDV...

Page 961: ...Each ATM channel has a channel code used as an index to the channel s connection table entry The first channel in the table has channel code one the second has channel code two and so on Codes of 255...

Page 962: ...ula for determining the real starting address for all internal and external connection table entries is as follows Connection table base address channel code 32 Thus the real starting address of the R...

Page 963: ...Time Stamp Offset 0x0A Offset 0x0C RBD_Offset Offset 0x0E Protocol Specific For AAL5 Section 30 10 2 2 1 AAL5 Protocol Specific RCT For AAL2 Section 32 4 4 1 AAL2 Protocol Specific RCT For AAL1 Secti...

Page 964: ...This is necessary because in UDC mode the user defined header which is part of the cell data is read using the same bus configuration byte ordering and bus type as the payload Therefore if data is pla...

Page 965: ...PowerQUICC II time stamp timer is sampled and written to this field See Section 14 3 8 RISC Time Stamp Control Register RTSCR 0x0C RBD_Offset RxBD offset from RBD_BASE Points to the channel s current...

Page 966: ...e current Rx buffer RBDCNT is initialized with MRBLR whenever the CP opens a new buffer 0x16 Reserved should be cleared 0x18 0 7 Reserved should be cleared 8 RXBM Receive buffer interrupt mask Determi...

Page 967: ...allowed cell rate never exceeds this value PCR uses the ATMF TM 4 0 floating point format 0x18 0 3 RDF Rate decrease factor for the current ABR channel Controls the decrease in cell transmission rate...

Page 968: ...handled in negative logic 0 empty 1 not empty 11 STF Structured format 0 Unstructured format is used 1 Structured format is used 12 15 Reserved should be cleared 0x10 0 3 SRTS_TMP Used by the CP to st...

Page 969: ...Reserved should be cleared 8 RXBM Receive buffer interrupt mask 0 The receive buffer event of this channel is disabled The event is not sent to the interrupt queue 1 The receive buffer event of this...

Page 970: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset 0x00 GBL BO DTB BIB AVCF ATT CPUU VCON INTQ Offset 0x02 INF ABRF AAL Offset 0x04 Tx Data Buffer Pointer TXDBPTR Offset 0x06 Offset 0x08 TBDCNT Offset 0x0A TB...

Page 971: ...ATM Controller and AAL0 AAL1 and AAL5 MPC8260 PowerQUICC II Family Reference Manual Rev 2 Freescale Semiconductor 30 51 Table 30 21 describes general TCT fields...

Page 972: ...ATM Controller and AAL0 AAL1 and AAL5 MPC8260 PowerQUICC II Family Reference Manual Rev 2 30 52 Freescale Semiconductor...

Page 973: ...CP clears TCT VCON Note When over subscribing UBR or UBR channels set AVCF so that the CPM does not become overloaded polling non active VCs 9 Reserved should be cleared 10 11 ATT ATM traffic type 00...

Page 974: ...from the data length field of the TxBD when a new buffer is open its value is subtracted for any transmitted cell associated with this channel 0x0A TBD_OffSe t Transmit BD offset Holds offset from TBD...

Page 975: ...The buffer not ready event of this channel is enabled 13 STPT Stop transmit Should be cleared initially When the host sets this bit the CP deactivates this channel and clears TCT VCON when the channe...

Page 976: ...ion using external logic If this mode is enabled the PowerQUICC II reads the SRTS from external logic and inserts it into four cells for which SN 1 3 5 or 7 The PowerQUICC II reads the new SRTS from e...

Page 977: ...l Specific TCT 30 10 2 3 6 VBR Protocol Specific TCTE Figure 30 34 shows the VBR protocol specific TCTE 0 7 8 9 10 11 12 15 Offset 0x10 0 CR10 ACHC Offset 0x12 Offset 0x14 Figure 30 33 AAL0 Protocol S...

Page 978: ...ermitted for this channel according to the traffic contract The relationship between the BT and the maximum burst size MBS is BT MBS 2 SCR PCR SCR 0x04 OOBR Out of buffer rate In out of buffer state w...

Page 979: ...et 0x06 0x1E Figure 30 35 UBR Protocol Specific TCTE Table 30 26 UBR Protocol Specific TCTE Field Descriptions Offset Bits Name Description 0x00 MCR Minimum cell rate for this channel MCR is in units...

Page 980: ...evious F RM cell was turned around this field is overwritten by the new RM cell s ER 0x02 CCR TA Current cell rate turn around cell Holds the CCR of the last received F RM cell If another F RM cell ar...

Page 981: ...ne 1 15 Reserved should be cleared 0x10 RCTS RM cell time stamp Used exclusively by the CP Initialize to zero 0x14 0 FRST First turn Used exclusively by the CP Indicates the first turn of a backward R...

Page 982: ...cit rate Holds the explicit rate value in cells sec of the current ABR channel ER is copied to the F RM cell ER field The user usually initializes this field to PCR ER uses the ATMF TM 4 0 floating po...

Page 983: ...TUC1 Total user cell 1 Count of CLP 1 user cells modulo 65 536 sent Should be cleared initially 0x06 TUC0 Total user cell 0 Count of CLP 0 user cells modulo 65 536 sent Should be cleared initially 0x...

Page 984: ...initialized as APCL_FIRST 8 x number_of_priorities 1 0x04 APCL_PTR Hword Address of current priority entry used by the CP User initialized with APCL_FIRST 0x06 CPS Byte Cells per slot Determines the...

Page 985: ...CPS is 8 CPS_ABR 0x03 0x0A LINE_RATE_AB R Hword ABR only The PHY line rate in cells sec represented in TM 4 0 floating point format User defined 0xC REAL_TSTP Word Real time stamp pointer used intern...

Page 986: ...emory among many ATM channels with variable data rates such as ABR channels 30 10 5 1 Transmit Buffer Operation The user prepares a table of BDs pointing to the buffers to be sent The address of the f...

Page 987: ...is the offset to the current BD from RBD_BASE and reads the next BD in the table If the BD is empty RxBD E 1 the CP continues receiving If the BD is not empty a busy condition has occurred and a busy...

Page 988: ...other buffer pointer from the free buffer pool and reception continues If the BD is not empty a busy condition occurs and a busy interrupt is sent to the event queue specifying the ATM channel code As...

Page 989: ...FCCE GBPB and a busy interrupt is sent to the interrupt queue specifying the ATM channel code associated with the pool Figure 30 44 Free Buffer Pool Structure Figure 30 45 describes the structure of a...

Page 990: ...ular table During initialization the host must clear all W bits in the table except the last one which must be set 3 I Red line interrupt Can be used to indicate that the free buffer pool has reached...

Page 991: ...D under core control 9 15 Reserved should be cleared 0x0C FBP_ENTRY Free buffer pool entry Initialize with the first entry of the free buffer pool Note that FBP_ENTRY must be reinitialized with the en...

Page 992: ...ent register when INT_CNT reaches the global interrupt threshold 4 L Last in frame Set by the ATM controller for the last buffer in a frame 0 Buffer is not last in a frame 1 Buffer is last in a frame...

Page 993: ...the CP once the BD is closed In the last BD of a frame DL contains the total frame length 0x04 RXDBPTR Rx data buffer pointer Points to the first location of the associated buffer may reside in intern...

Page 994: ...nd is determined only by the W bit The current table overall space is constrained to 64 Kbytes 3 I Interrupt 0 No interrupt is generated after this buffer has been used 1 An Rx buffer event is sent to...

Page 995: ...current table cannot exceed 64 Kbytes 3 I Interrupt 0 No interrupt is generated after this buffer has been used 1 An Rx buffer event is sent to the interrupt queue after the ATM controller uses this b...

Page 996: ...stored in the buffer the AAL0 BD size is always 8 bytes 30 10 5 10 AAL5 TxBDs Figure 30 50 shows the AAL5 TxBD Table 30 38 describes AAL5 TxBD fields Offset 0x08 Extra Cell Header Used to store the us...

Page 997: ...his buffer is serviced FCCE GINTx is set when the INT_CNT counter reaches the global interrupt threshold 4 L Last in frame Set by the user to indicate the last buffer in a frame 0 Buffer is not last i...

Page 998: ...ld be cleared 2 W Wrap final BD in table 0 Not the last BD in the TxBD table 1 Last BD in the TxBD table After this buffer is used the CP sends outgoing data from the first BD in the table the BD poin...

Page 999: ...om the first BD in the table the BD pointed to by the channel s TCT TBD_BASE The number of TxBDs in this table is determined by the W bit The current table is constrained to 64 Kbytes 3 I Interrupt 0...

Page 1000: ...tion table pointed to by AAL1_SNPT_BASE in the ATM parameter RAM resides in dual port RAM and is used for AAL1 only The table should be initialized according to Figure 30 54 Offset 0x08 Extra Cell Hea...

Page 1001: ...sent to the core using a down counter in the interrupt queue s parameter table see Section 30 11 3 For each event sent to an interrupt queue a counter that has been initialized to a threshold number...

Page 1002: ...e 30 11 2 Interrupt Queue Entry Each one word interrupt queue entry provides detailed interrupt information to the host Figure 30 56 shows an entry Table 30 42 describes interrupt queue entry fields 0...

Page 1003: ...his interrupt is sent only if frame transmission is started In this case an abort frame transmission is sent last cell with length 0 the channel is taken out of the APC and the TCT VCON flag is cleare...

Page 1004: ...ues a global interrupt FCCE GINTx 0x0C INTQ_ENTRY Word Interrupt queue entry Must be initialized to the entry pointed to by INTQ_PTR which is initially the first empty entry of the queue Note that aft...

Page 1005: ...TxADD 4 is the msb RxDATA 15 0 7 0 Carries receive data from the PHY to the ATM controller RxDATA 15 7 is the msb when using UTOPIA 16 8 RxDATA 0 is the lsb RxSOC Receive start of cell Asserted by th...

Page 1006: ...msb TxDATA 0 is the lsb TxSOC Transmit start of cell Asserted by an ATM controller as the first byte of a cell is sent on the TxDATA lines TxENB Transmit enable An input to the ATM controller It is a...

Page 1007: ...The following sections describe the configuration of the registers in ATM mode RxENB Receive enable Asserted by the master device to signal the slave to sample the RxDATA and RxSOC signals RxCLAV Rec...

Page 1008: ...S Reset 0000_0000_0000_0000 R W R W Addr 0x11306 FPSMR1 0x11326 FPSMR2 0x11346 FPSMR3 Figure 30 59 FCC ATM Mode Register FPSMR Table 30 47 FCC ATM Mode Register FPSMR Bits Name Description 0 3 TEHS Tr...

Page 1009: ...ed in both single Clav and direct polling modes PHY ID Multiple PHY slave mode only Determines the PHY address of the ATM controller when configured as a slave in a multiple PHY ATM port Note For IMA1...

Page 1010: ...ero to the PHY specified in LAST PHY When a PHY is selected the UTOPIA interface continues to poll the next PHY in order 1 Fixed priority Polling is done from PHY zero to the PHY specified in LAST PHY...

Page 1011: ...nsmit internal rate underrun A cumulative lag of seven cells has formed between the programmable rate and the actual rate for a specific Phy A transmit internal rate counter expired and a cell was not...

Page 1012: ...The source clock of the internal rate timers is supplied by one of four baud rate generators selected in CMXUAR see Section 16 4 1 CMX UTOPIA Address Register CMXUAR Note that in slave mode FTIRRx_PHY...

Page 1013: ...tion 30 16 1 Using Transmit Internal Rate Mode 30 14 ATM Transmit Command The CPM command set includes an ATM TRANSMIT that can be sent to the CP command register CPCR described in Section 14 4 1 The...

Page 1014: ...le SRTS 0 is inserted into the cell with SN 7 SRTS 3 is inserted into the cell with SN 1 For every eighth AAL1 CES SAR PDU the SRTS logic Table 30 50 COMM_INFO Field Descriptions Offset Bits Name Desc...

Page 1015: ...3 msb The SRTS is synchronized with the sequence count cycle SRTS 3 is read from the cell with SN 1 and SRTS 0 is read from the cell with SN 7 The SRTS PLL makes periodic clock adjustments based on t...

Page 1016: ...C data structure improves CPM performance Cells per slot CPS defines the maximum number of ATM cells allowed to be sent during a time slot See Section 30 3 3 1 Determining the Cells Per Slot CPS in a...

Page 1017: ...PowerQUICC II are as follows AAL1 Reassembly Reassembles PDU directly to external memory Supports partially filled cells configurable on a per VC basis Sequence number SN protection CRC 3 and parity c...

Page 1018: ...run the ATM receiver discards incoming cells until the MCC transmitter empties enough buffers for the receiver to restart Supports common channel signaling CCS Supports channel associated signaling CA...

Page 1019: ...ght successive cells The transmitter will insert the structured pointer at the first opportunity into a cell with an even sequence count SC When the end of the structure is not present in the current...

Page 1020: ...algorithm see Section 31 6 1 The Three States of the Algorithm handles the lost or misinserted cells This algorithm can detect one lost or misinserted cell and maintain synchronization If more than on...

Page 1021: ...ell with a valid sequence number SN field When one arrives the receiver leaves the hunt state and begins receiving incoming cells In structured AAL1 format when the receive process begins the receiver...

Page 1022: ...ready bit TxBD R Similarly when an ATM receive buffer is full and its RxBD is closed the core services the ATM controller s interrupt by copying the ATM receive buffer pointer to an MCC TxBD and setti...

Page 1023: ...ansmitter then initialize the ATM receiver This way the MCC transmitter sends idle data 0xFF until the ATM receiver fills enough buffers to reach the MCC start threshold The receiver is effectively fi...

Page 1024: ...threshold pointers and a counter for each ATM TDM VC to super channel connection Before a buffer not ready event ATM to TDM data forwarding occurs at the MCC transmitter the MCC buffer pointer reaches...

Page 1025: ...verrun MCCE GOV conditions are errors that need CPU intervention because it is not known which channels are affected The CPU should accordingly reinitialize the transmit parameters and or the receive...

Page 1026: ...the superframe block boundary At the ATM side the structured block size should be set to the superframe block size plus the size of the CAS block so that the structured pointer inserted by the ATM co...

Page 1027: ...the internal CAS block depicted in Figure 31 8 The CRT entries should be initialized only once before the ATM channel is enabled receiver or transmitter The number of entries that should be initializ...

Page 1028: ...AL1 CES CAS Routing Table Entry 0 1 2 3 7 Offset 0x00 W F S Signaling offset pointer SOP 0 0 0 0 0 0 0 0 0 XXXX 0 1 ABCD F S 0 Example of one MCC super channel in ESF framing T1 containing 4 TDM slots...

Page 1029: ...g a separate TDM When a super frame is received the MCC should be triggered with a super frame multi frame SYNC from the external framer The incoming CAS block should be captured by the MCC only once...

Page 1030: ...ormation from the end of an AAL1 super frame depicted in Figure 31 3 and places it in the internal CAS block using the receive CAS routing table All AAL1 functions operate normally AAL1 PDU header ver...

Page 1031: ...mon BD table at a slower rate than it is being filled by the ATM receiver In this case the ATM write pointer meets the MCC read pointer and a BSY state is declared an entry is added to the ATM interru...

Page 1032: ...ation need only convert this value into an SRTS format Figure 31 14 shows the 8 byte data structure used to implement ATM to TDM slip control Three of the bytes are unused Figure 31 14 Data Structure...

Page 1033: ...n condition occurs This field should be defined by the user during the channel initialization 8 15 ASTRT ATM start threshold This threshold determines the Time interval that will take the ATM controll...

Page 1034: ...6 MCC_Start ATM Rx pointer BD table W BD 1 BD 2 BD 3 BD 4 BD 5 MCC Tx pointer 0 0 0 0 1 ATM to TDM Step 3 Because the MCC is reading the data faster than the ATM CESAC falls to the CESAC 1 MCC_Start 3...

Page 1035: ...1 BD 2 BD 3 BD 4 BD 5 MCC Tx pointer 0 0 1 1 1 ATM to TDM Step 3 The MCC reads the data slower than the ATM fills it The ATM points to the CESAC 4 MCC_Start 3 MCC_Stop 1 BD 6 1 BD 7 0 ATM_Start 5 ATM...

Page 1036: ...r When a valid cell is detected the algorithm switches to the Sync state and delivers the current cell to the Rx buffer 2 Sync The Sync state is the steady state of the algorithm In this state any rec...

Page 1037: ...rity error the pointer state machine switches to Pre Hunt Mode If the cell status is not valid i e Tag Drop or Dummy and it supposed to carry a pointer the pointer declared a mismatch and the pointer...

Page 1038: ...iguration structures shown in the next tables The following table includes fields for ATM operation generally and AAL1 CES fields particularly Note that some of the values must be initialized by the u...

Page 1039: ...DC extra header Should be an even address If RCT BO 01 UEAD_OFFSET should be in little endian format For example if UEAD entry is the first half word of the extra header in external memory UEAD_OFFSET...

Page 1040: ...d be 16 byte aligned 0xA0 IDLE UNASSIGN_BASE Hword Idle unassign cell base address Points to dual port RAM area contains idle unassign cell template little endian format Should be 64 byte aligned User...

Page 1041: ...d 0xd0 OCASSR Byte Outgoing CAS Status Register See Section 31 10 Outgoing CAS Status Register OCASSR 0xE0 TCELL_TMP_BASE _EXT Word Transmit Cell Temporary base address 64 byte aligned Points to an ex...

Page 1042: ...OTE For an active channel the CP uses a burst cycle to fetch the 32 byte RCT and writes back only the first 24 bytes Table 31 5 describes RCT fields 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset 0x00 G...

Page 1043: ...use they share the same AAL1_Ext_STATT_BASE parameter 8 9 Reserved should be cleared during initialization 10 SEGF OAM F5 segment filtering 0 Do not send cells with PTI 100 to the raw cell queue 1 Sen...

Page 1044: ...E RxBD base Points to the first BD in the channel s RxBD table The 8 most significant bits of the address are taken from BD_BASE_EXT in the parameter RAM The four least significant bits of the address...

Page 1045: ...y 0 RxBD E is interpreted normally 1 empty 0 not empty 1 RxBD E is handled in negative logic 0 empty 1 not empty Note that in CAS mode CESM 1 this bit must be set by the user see Section 31 4 1 Automa...

Page 1046: ...d must be initialized by the user in CES mode only See Section 31 4 7 Mapping VC Signaling to CAS Blocks 8 RXBM Receive buffer interrupt mask 0 The receive buffer event of this channel is disabled The...

Page 1047: ...BIB ATT AVCF VCON INTQ Offset 0x02 AAL Offset 0x04 Tx Data Buffer Pointer TXDBPTR Offset 0x06 Offset 0x08 TBDCNT Offset 0x0A TBD_OFFSET Offset 0x0C Rate Remainder PCR Fraction Offset 0x0E PCR Offset 0...

Page 1048: ...d the PCR fraction Other traffic parameters are not used 01 Peak and sustain cell rate pacing VBR traffic The APC performs a continuous state leaky bucket algorithm GCRA to pace the channel sustain ce...

Page 1049: ...Initialize to 0 null pointer 0x18 ATMCH ATM cell header Holds the full 4 byte ATM cell header of the current channel The transmitter appends ATMCH to the cell payload during transmission 0x1C 0 1 Res...

Page 1050: ...I supports SRTS generation using external logic If this mode is enabled the PowerQUICC II reads the SRTS from external logic and inserts it into four cells for which SN 1 3 5 or 7 The PowerQUICC II re...

Page 1051: ...S block The starting address of the table is IN_CAS_BLOCK_BASE ICASB 32 See Section 31 4 7 1 CAS Routing Table for more details Note that the RCT and TCT use the same CAS routing table CRT SRTS_TMP ap...

Page 1052: ...BD for each buffer When the receiver or transmitter completes writing or reading the buffer it moves to the next buffer in the list and optionally issues an interrupt 31 11 1 Transmit Buffer Operatio...

Page 1053: ...RxBD E 1 the CP continues receiving If the BD is not empty a busy condition has occurred and the ATM receiver optionally issues an interrupt to the event queue Note that when the ATM receiver is in CE...

Page 1054: ...east 44 octets except last buffer in frame Double word aligned At least 44 octets No requirement AAL1 AAL1 CES Multiple of 8 octets No requirement Multiple of 8 octets No requirement AAL0 52 64 octets...

Page 1055: ...and is determined only by the W bit The current table overall space is constrained to 64 Kbytes 3 I Interrupt 0 No interrupt is generated after this buffer has been used 1 An Rx buffer event is sent t...

Page 1056: ...able After this buffer is used the CP sends outgoing data from the first BD in the table the BD pointed to by the channel s TCT TBD_BASE The number of TxBDs in this table is determined only by the W b...

Page 1057: ...ro 0x04 TXDBPTR Tx data buffer pointer Points to the address of the associated buffer The buffer may reside in either internal or external memory This value is not modified by the CP 0 1 2 3 7 8 9 10...

Page 1058: ...ot ready Set when a transmit buffer not ready interrupt is issued This interrupt is issued when the CP tries to open a TxBD that is not ready R 0 This interrupt is sent only if TCT BNM 1 This interrup...

Page 1059: ...set 0x12 0x000C Offset 0x14 0x0006 Offset 0x16 0x0001 Offset 0x18 0x0005 Offset 0x1A 0x0002 Offset 0x1C 0x0008 Offset 0x1E 0x000F Figure 31 31 AAL1 Sequence Number SN Protection Table Table 31 14 AAL1...

Page 1060: ...does not use super frame synchronization for the data flow in ATM to TDM and TDM to ATM interworking However for the signaling flow the PowerQUICC II uses the super frame sync signal to know when to s...

Page 1061: ...at a higher rate than the MCC super channel rate We expect that the jitter caused by the APC traffic reshaping will depend on the ATM channel rate PCR PCR_FRACTION Figure 31 32 illustrates this timing...

Page 1062: ...ATM AAL1 Circuit Emulation Service MPC8260 PowerQUICC II Family Reference Manual Rev 2 31 46 Freescale Semiconductor...

Page 1063: ...d data structures of AAL2 CPS CPS switching and SSSAR and should be used as a supplement to Chapter 30 ATM Controller and AAL0 AAL1 and AAL5 32 1 Introduction AAL2 enables the multiplexing of voice an...

Page 1064: ...specific segmentation and reassembly sublayer SSSAR Service specific transmission error detection sublayer SSTED Service specific assured data transfer sublayer SSADT Figure 32 2 AAL2 Sublayer Structu...

Page 1065: ...The priority mechanism provides for TX queues having equal or differing priorities The SSSAR TX queues can be prioritized flexibly among the CPS TX queues Timer_CU support NoSTF mode support Support f...

Page 1066: ...into an SSSAR SDU A separate queue for every PHY VP VC CID Perform all the above mentioned CPS receiver functions A Ras_Timer mode is provided When the Ras_Timer expires the buffer is closed with a t...

Page 1067: ...lds the queue pointer and parameters to manage the queue When the transmitter fetches a packet out of an SSSAR TX Queue it usually takes out of the SSSAR buffer a number of octets equal to TxQD Seg_Le...

Page 1068: ...re 32 4 Round Robin Priority The transmitter steps from one TxQD to the next along the queue links The TCT MaxStep parameter limits the number of TX Queues that the transmitter visits during a cell ti...

Page 1069: ...ts the number of data octets sent with each ATM cell Partial fill mode assures that packets are not split over two cells unless the first packet of the cell is greater than 47 bytes In partial fill mo...

Page 1070: ...AAL2 Tx Data Structures The following sections describe the transmit connection tables TCT and the structures in which CPS packets and SSSAR SDUs are stored in memory Cell STF AAL2 AAL2 AAL2 AAL2 pack...

Page 1071: ...P fetches the TCT 32 bytes using burst cycle and writes back only the first 24 bytes Table 32 1 describes the AAL2 TCT fields 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset 0x00 GBL BO DTB BIB AVCF PFM...

Page 1072: ...ATM AAL2 MPC8260 PowerQUICC II Family Reference Manual Rev 2 32 10 Freescale Semiconductor...

Page 1073: ...e transmission after the host adds buffers for transmission a new ATM TRANSMIT command is needed which can be issued only after the CP clears the VCON bit Bit 13 9 PFM Partial fill mode See Section 32...

Page 1074: ...xQD 0x0C 0 7 Rate Remainder Rate remainder Used by the APC to hold the rate remainder after adding the pace fraction to the additive channel rate Should be cleared during initialization by the user 8...

Page 1075: ...ode PFM Specifies the maximum number of packet bytes allowed in a CPS PDU The range 1 48 are valid values If PFT 48 in partial fill mode performance is adversely affected When not in partial fill mode...

Page 1076: ...or this queue is enabled 9 SW Switching queue 0 Normal TX Queue 1 This TxQD handles a switching queue The receiver and transmitter share this queue 10 HEC HEC calculation 0 Transmitter calculates the...

Page 1077: ...ounts down with every packet sent This can have various purposes such as evaluating the packet rate that is transmitted from this queue 0x0C NextQueue Points to the next TxQD to be serviced after this...

Page 1078: ...ss of the CM bit setting 2 W Wrap final BD in table 0 This is not the last BD in the TxBD table 1 This is the last BD in the TxBD table After this buffer is used the CP transmits outgoing data for thi...

Page 1079: ...inked list of TxQDs as described in Section 32 3 2 Transmit Priority Mechanism The SSSAR TxQD is located in the dual port RAM in a 32 byte aligned address Table 32 4 describes the SSSAR TxQD fields 0...

Page 1080: ...32 10 10 INF Indicates the current state of the frame 0 The next packet will be the first of a new frame 1 Currently in the middle of the frame 11 CPS Sublayer type For an SSSAR TxQD this field must b...

Page 1081: ...R is set 1 CM Continuous mode 0 Normal operation 1 The CP does not clear R after this BD is closed allowing the associated buffer to be retransmitted automatically when the CP next accesses this BD H...

Page 1082: ...ed The receiver now begins the process of extracting new CPS packets out of the cell with another round of error checking The receiver examines each CPS packet header for the following errors Incorrec...

Page 1083: ...SSSAR SDU If this time limit is exceeded the receiver closes the current buffer with RxBD RxError TE 01 Ras_Timer expired and starts a new SSSAR frame with the next packet When a buffer is closed wit...

Page 1084: ...PS TxQD into which this packet is saved and later sent by the transmitter The TxQD pointer is responsible for the actual PHY VP VC switching The TxQD pointed to by the switch RxQD s should have TxQD S...

Page 1085: ...and the UP bit remains set In such a case the transmitter skips this BD and proceeds to the next one If for any reason the receiver that was in the middle of the BD stopped receiving traffic the UP bi...

Page 1086: ...ATM VC Figure 32 15 shows the AAL2 specific RCT NOTE For an active channel the CP uses a burst cycle to fetch the 32 byte RCT and writes back only the first 24 bytes Table 32 6 describes the AAL2 RCT...

Page 1087: ...ot send cells with PTI 100 to the raw cell queue 1 Send cells with PTI 100 to the raw cell queue 11 ENDF OAM F5 end to end filtering 0 Do not send cells with PTI 101 to the raw cell queue 1 Send cells...

Page 1088: ...ct as if the receiver is stuck in error condition and proceed to the next BD in the BD ring This parameter is valid in switch mode only and should be programmed to a higher value than the ratio betwee...

Page 1089: ...external RxQDs Offsets between 0 511 belong to the 2048 byte internal RxQD table It is recommended to have as many RxQDs as possible in the internal table Note that the first 32 bytes of the internal...

Page 1090: ...11 Reserved should be cleared during initialization 12 RBM Receive buffer mask 0 Disable receive buffer interrupt 1 Enable receive buffer interrupt 13 Reserved should be cleared during initialization...

Page 1091: ...t accesses this BD However the E bit is cleared if an error occurs while receiving regardless of the CM bit setting 2 W Wrap final BD in table 0 This is not the last BD in the RxBD table 1 This is the...

Page 1092: ...user Description 0x00 0 7 TX CID Translation CID The received CID is saved in a TX Queue with this new CID number 8 11 Reserved should be cleared during initialization 12 RBM Receive buffer mask 0 Di...

Page 1093: ...een received 1 if R E 1 a receive error occurred that caused this packet to be uncompleted The receive error type is reported to the interrupt queue The transmitter will skip this BD when in this stat...

Page 1094: ...scription 0x00 0 10 Reserved should be cleared during initialization 11 RasT Ras Timer enable 0 Ras Timer disabled Time Stamp field is still valid 1 Ras Timer enabled The Ras Timer duration is set by...

Page 1095: ...d for reassembly timeout of the SSSAR SDU Whenever the first packet of an SSSAR SDU arrives the timestamp timer is sampled and stored here regardless of the RasT bit 0x10 Reserved should be cleared du...

Page 1096: ...W bit The current table cannot exceed 64 Kbytes 3 I Interrupt 0 No interrupt is generated after this buffer has been serviced 1 An Rx buffer event is sent provided that RxQD RBM is set to the interru...

Page 1097: ...s reserved dual port RAM area used by the CP Should be 64 byte aligned User defined Recommended address space 0x3000 0x4000 or 0xB000 0xC000 0x44 UDC_TMP_BASE Hword UDC mode only Points to a total of...

Page 1098: ...ent to the raw cell queue VCI 3 is associated with VCI_Filtering 3 VCI 15 is associated with VCI_Filtering 15 VCI_Filtering 0 2 5 should be zero See Section 30 10 1 2 VCI Filtering VCIF 0x84 GMODE Hwo...

Page 1099: ...r defined 0xB4 RxQD_Base_Ext Word Points to the base address of the external RxQD table The actual address of the first RxQD in the table is RxQD_Base_Ext 512 4 User defined 0xB8 RX_UDC_Base Word Vali...

Page 1100: ...f that VC are discarded UDC extended address mode UEAD is not affected The UDC header of a specific AAL2 receive VC is located at the following address RX_UDC_Base CH 16 where CH is the ATM channel nu...

Page 1101: ...TxQD BNM 1 The interrupt has an associated channel code and CID Note The CID number that is placed in the interrupt queue is the one currently located in the last BD Because the CID is not updated wh...

Page 1102: ...tialization the host must clear all W bits in the table except the last one which must be set 3 10 CID CID number Equals zero This exception applies to the whole cell 11 Reserved 12 15 Error_Code A re...

Page 1103: ...is available only on the MPC8264 and the MPC8266 Refer to www freescale com for the latest RAM microcode packages that support enhancements This chapter provides specifications for the inverse multipl...

Page 1104: ...ICP cell insertion removal communication of control and framing information Cell rate decoupling insertion of filler cells when ATM layer cells are unavailable IMA frame synchronization finding IMA fr...

Page 1105: ...ion Version 1 1 AF PHY 0086 001 The ATM Forum Technical Committee Inverse Multiplexing for ATM IMA Specification Version 1 0 AF PHY 0086 000 33 1 2 IMA Versions Supported The IMA microcode supports IM...

Page 1106: ...e detailed information refer to Section 33 4 8 2 IDCR FCC Parameter Shadow 33 2 IMA Protocol Overview This section describes the IMA protocol not the PowerQUICC II s IMA microcode 33 2 1 Introduction...

Page 1107: ...y over the multiple links 33 2 2 IMA Frame Overview The IMA interface periodically transmits special cells that contain information that permit reconstruction of the ATM cell stream at the receiving e...

Page 1108: ...nsistent average data rate over the links of the group Furthermore IMA must compensate for potential differences in delay between the links of the group Per the IMA specification the allowable delay d...

Page 1109: ...in an IMA group e g one link is slightly faster than the other The insertion of additional ICP cells to compensate for timing differences between links is called a stuff event The transmitter is respo...

Page 1110: ...Cell 4 Cell n IMA RX Function Fast Communication Controller acting as a Virtual PHY Cell 1 Cell n Cell 2 Phy 1 Phy 2 Phy n Cell n 1 ATM TX Function Cell 1 Cell 2 Cell 3 Cell 4 Cell n IMA TX Function F...

Page 1111: ...Cell 4 Cell n IMA RX Function Fast Communication Controller acting as a Virtual PHY Cell 1 Cell n Cell 2 Phy 1 Phy 2 Phy n Cell n 1 ATM TX Function Cell 1 Cell 2 Cell 3 Cell 4 Cell n IMA TX Function F...

Page 1112: ...explains the architecture of the receive and transmit IMA microcode tasks 33 3 1 IMA Function Partitioning The IMA microcode performs only those functions with regular critical real time demands The...

Page 1113: ...articularly on the independent transmit clock ITC mode of IMA Differences in behavior when common transmit clock CTC mode is used are discussed at the end of this section Only one cell scheduler known...

Page 1114: ...the APC scheduling algorithm to find the next scheduled ATM channel 2 Distribute either An ICP cell A filler cell if filler only or active with nothing scheduled in the APC A data cell if a channel i...

Page 1115: ...t RAM microcode package This optional feature allows the user to change the IMA APC behavior upon TRL request When enabled the TRL request will pass a programmable number of cells to the Tx queue of t...

Page 1116: ...e just shown with respect to the overall queue depth available with the extraction pointer always shown at the bottom of the queue This is done only for the purpose of ease of illustration In reality...

Page 1117: ...on pointer Tx Queue Queue insertion pointer Transmitted by non TRL task Normal Wander zone floats between these two positions wrapped Depth is 4 x creeps up such that it Queue extraction pointer Tx Qu...

Page 1118: ...ly i e may have constant offsets and will definitely not be serviced simultaneously Queue extraction pointer Tx Queue Transmitted by non TRL task Normal Wander zone Queue extraction pointer Tx Queue B...

Page 1119: ...r The cell reception task services requests from the links via the UTOPIA multi PHY interface and the FCC maintains the link state and if the link and group state dictates writes the received cells in...

Page 1120: ...oftware to initialize IMA links and groups and to manage transitions between link and group states The cell reception task centers around a four state link state machine Microcode tasks are performed...

Page 1121: ...incoming cells keep only ICP cells discard other cells Configuration to reach to move to next state Group Link initialized by the driver based on the ICP content Link s M value ICP screen incoming cel...

Page 1122: ...Inverse Multiplexing for ATM IMA MPC8260 PowerQUICC II Family Reference Manual Rev 2 33 20 Freescale Semiconductor...

Page 1123: ...Inverse Multiplexing for ATM IMA MPC8260 PowerQUICC II Family Reference Manual Rev 2 Freescale Semiconductor 33 21 Figure 33 11 IMA Microcode Receive Process...

Page 1124: ...link delay synchronization algorithm If the link enters this state while the group is already activated per the link addition slow recovery LASR procedure of the IMA standard it performs the added li...

Page 1125: ...ered IMA data cell rate IDCR During group startup the microcode recovers the PHY clock rate of the TRL from the average period between requests from the TRL PHY It does this by averaging the differenc...

Page 1126: ...te AAL or OAM function If the on demand cell processing activation function is used then when the cell processing task is triggered it will extract cells in order from the delay compensation buffers u...

Page 1127: ...ed IMA group IMA Link Receive Table and IMA Link Transmit Table entries include parameters that define the receive and transmit states and settings of the associated IMA link Optional IDCR Table that...

Page 1128: ...r a standard FCC in that they contain 64 byte aligned addresses of regions of DPRAM for temporary cell storage However the 4 bytes leading and 4 bytes following the region indicated by TCELL_TMP_BASE...

Page 1129: ...Version 1 0 or 1 1 0x00 0x2F IMAFILLERPLD 48 Bytes 0x30 FILLTAG Byte Tag indicating that the filler template is a filler cell Program to zero 0x31 TQ_SIZE Byte Transmit queue size Recommended value i...

Page 1130: ...e aligned 0x4E IMALINKT_RX Hword Offset of IMA link receive table in DPRAM Must be 32 byte aligned 0x50 IRLINKSTAT Hword Offset of the optional IMA link receive statistics table in DPRAM Must be 8 byt...

Page 1131: ...ed at the word which immediately precedes the 128 byte aligned region defined by IMAROOT Thus it is located at offset 0x04 from base of IMAROOT table 0 1 2 3 4 5 6 7 Field IRSE IQB DSB INTQ Figure 33...

Page 1132: ...ld be initialized to zero at group start up 0x06 TMCTR Byte Transmit IMA M counter Microcode managed parameter Tracks IMA frame boundaries Increments once per round robin distribution of cells to the...

Page 1133: ...CTC ICPC Figure 33 14 IMA Group Transmit Control IGTCNTL Table 33 6 IGTCNTL Field Descriptions Bits Name Description 0 2 Reserved 3 4 TXSC Transmit status control Sets the transmit mode of the IMA gr...

Page 1134: ...IGTSTATE Table 33 7 IGTSTATE Field Descriptions Bits Name Description 0 TSTF TRL stuff flag Microcode managed parameter Indicates that the next ICP cell on the TRL will be part of a stuff event Initia...

Page 1135: ...of transmission of the cell The transmission of the cell is per the ATM standard Reflecting this byte swap the offset column gives the offset in DPRAM from the ICP template base Table 33 8 Transmit G...

Page 1136: ...nt this field in the new ICP template whenever a new ICP template is created 0x0B Link Stuff Indication Byte Microcode managed area Microcode will program this field dynamically 0x0C RX TEST PATTERN B...

Page 1137: ...e Status and control of link with LID 21 0x27 LINK 20 INFO Byte Status and control of link with LID 20 0x28 LINK 27 INFO Byte Status and control of link with LID 27 0x29 LINK 26 INFO Byte Status and c...

Page 1138: ...last ICP cell received by this group 0x08 DCBLNK Hword Pointer to link entry in group order table currently in use Microcode managed parameter Initialize to value of RGRPORDER0 at group startup 0x0A...

Page 1139: ...tialize to zero at group startup 0x24 LINK_LD Word Bit array identifying which of the added links in this group has a Longer propagation Delay LD than any of the existing links A 1 in the correspondin...

Page 1140: ...t skew between links of a group 2 5 per the IMA standard An optimal value for STALL_THR will be great enough to produce no link stall events in normal operation but low enough to detect a failed link...

Page 1141: ...ing data cells 1XReserved Defaults to Filler Mode 5 IDCR IDCR recovery enable Selects the mode of the receive process activation function 0 On demand cell processing 1 IDCR regulated cell processing 6...

Page 1142: ...ld be toggled When the current round robin cell extraction process completes the next process will use the new table This table alone defines the order of cell extraction from the delay compensation b...

Page 1143: ...yte IMA link transmit state Microcode managed parameter Initialize to zero at link startup 0x02 LICPOS Byte Link ICP offset Determines the position of the ICP cell within the IMA frame Program in the...

Page 1144: ...us of transmit interrupt events 0x12 LSHC Byte Stuff holdoff counter Maintains the minimum five frame spacing between stuff events for non TRL links Must be initialized to zero Set to 4 by the microco...

Page 1145: ...the next ICP cell on this link will be part of a stuff event Initialize to zero at link startup 1 LIMSTF Link imminent stuff flag Microcode managed parameter Indicates that an upcoming stuff event wi...

Page 1146: ...errun events are masked when this bit is set in order to avoid a flood of interrupts This bit can be used to distinguish a temporary underrun condition which could be caused by a rate differential bet...

Page 1147: ...A receive interrupt mask Has the same format as the IMA interrupt queue entry however only receive related bits are relevant Setting a bit enables the associated interrupt clearing a bit masks it For...

Page 1148: ...rol Sets the receive mode of the IMA link 00 Filler mode The IMA link processes only ICP cells Data cells are replaced with filler cells 01 Active mode The IMA link is capable of receiving data cells...

Page 1149: ...nt 01 IMA presync 1x IMA sync 3 MASK_ERR Mask Error Microcode managed parameter Initialize to zero at link startup 4 STFEX Stuff cell expected Microcode managed parameter Initialize to zero at link st...

Page 1150: ...s defined by their start and end pointers For the transmit queue of the timing reference link TRL the queue must consist of a minimum of four buffers although it may consist of five buffers if consist...

Page 1151: ...CB defined by DCBEP DCBSP x 16 must be an integer multiple of the IMA frame length in bytes M x 64 Furthermore the DCBSP must be aligned on a M x 64 byte boundary For example if M 64 then DCBSP must b...

Page 1152: ...ted as normal receive events and should therefore go to the interrupt queue allocated for receive events 33 4 7 1 IMA Interrupt Queue Entry The format for the IMA interrupt queue entries is shown in F...

Page 1153: ...st This interrupt is issued when a link in a group with IGRSTATE GDSS 11 loses synchronization and the link enters HUNT state at the IFSM 10 LS Link stalled A link in the round robin cell extraction p...

Page 1154: ...ster clock frequency provides greater resolution in determining and reconstructing the IDCR However an IDCR master clock frequency that is too high will consume too much CPM processing power and will...

Page 1155: ...ust be directed to another dedicated interrupt queue COMM_INFO on the shadow page is unused ATM commands issued will use the COMM_INFO fields on the FCC parameter page INT_RCT_BASE and EXT_RCT_BASE sh...

Page 1156: ...IDCR IMA Root Parameters1 1 Boldfaced entries indicate parameters that must be initialized by the user All other parameters are managed by the microcode and should be initialized to zero unless other...

Page 1157: ...ssociated IDMAx bit in the SIPNR_L register The fields of the IDSR and IDMR registers are shown in Figure 33 30 Note that INTO1 GRLI and INTO0 GBPB occupy the same bits in the register Events of eithe...

Page 1158: ...buffer pool s RLI flag is set The RLI flag is also set in the free buffer pool s parameter table 7 INTO0 GBPB INTO0 Interrupt queue overflow 1 See INTOx above GBPB Global buffer pool busy interrupt G...

Page 1159: ...R SCR OOBR BT MCR and MDA 33 4 9 2 Programming for ABR ABR channels are a special case in that they are not programmed as a percentage of the physical line rate as inferred from the period of requests...

Page 1160: ...rQUICC II IMA data structures establishing and tearing down connections handling of alarms keeping statistics and controlling protocol state machines The IMA microcode interfaces to the software imple...

Page 1161: ...interaction with the ATM channels is the same as for non IMA operation e g host commands RCT TCT parameters buffer descriptors interrupts 33 5 3 Software Responsibilities The following functions are t...

Page 1162: ...ceive channel for ICP OAM cells such that all links in the group point to the same channel Control link operation via ILRCTNL RXSC in coordination with link and group states 33 5 3 4 Receive Group Sta...

Page 1163: ...up Symmetry Control All types of group symmetry operation and configuration are supportable This is facilitated by the ability to independently enable disable links via RXPHYEN and TXPHYEN and to cont...

Page 1164: ...receive and transmit event counters according to severely errorred seconds SES condition via ILRCNTL SES and ILTCNTL SES 33 5 3 13 SNMP MIBs Control interface and statistics information should be prov...

Page 1165: ...p report changed ICP cells to a single channel either by changing RICPCH for all the links to be the same or by clearing the MON_ICP bit ILRCNTL MON_ICP 0 Note at least 1 link in the group must have t...

Page 1166: ...e establishment of a group with X links involves the exchange of ICP cells between the Near End Initiator and the Far End Responder In any case both ends must start with a group of X potential links c...

Page 1167: ...xception is generated At this point ATM stream reconstruction can take place In order for ATM stream reconstruction to be performed by the PowerQUICC II the user must switch all links in the group to...

Page 1168: ...t we have a frame synchronized link we can proceed to allow the link to be delay synchronized Indicate that this is a new link GDS reconstruction function by inverting the current add new bit value IL...

Page 1169: ...ble entries Aside from the normal exchange of ICP cells by the state machines at the FE and NE the following steps should be followed In general a link entry is removed from the existing list of link...

Page 1170: ...A Group Transmit Table Entry IGTTE TGRPORDER New Table Offset 3 Decrement the number of links in the group IGTTE TNUMLINKS 1 4 Inhibit transmission of cells over dropped link in the IMA Root Table TXP...

Page 1171: ...able by inverting the current GOTP value IGRCNTL GOTP x 4 Increment RNUMLINKS in the group receive table 5 The Stall Threshold needs to be recalculated This parameter defines the acceptable tolerance...

Page 1172: ...ce when operating in IMA mode It is recommended that all events be handled via an exception interrupt service routine ISR as the response time inherent with interrupt driven events should diminish the...

Page 1173: ...expected IFSN value for a number GAMMA 2 of consecutive frames If this condition persists the link should be removed The threshold that would trigger the removal of the link is system specific The IFS...

Page 1174: ...quest to perform the test pattern to the FE the NE software must wait for the TX test pattern to be echoed back received in the RX Pattern field of the ICP cell any of the active links in the group ca...

Page 1175: ...reconstruction These steps should only be performed once 1 Configure the base offset of the IDCR Table in the IMA Root table IMAROOT IDCR_BASE x 2 Reset to zero the IDCR tick counter IMAROOT IDCRTICK...

Page 1176: ...IDCR_LAST 2 3 After GDS has been achieved the software can now read the captured TRLR value see IGRTE TRLR At this point the group s corresponding IDCR Table Entry can be programmed IDCRCNT and IDCRR...

Page 1177: ...tion of the end to end channel The end to end channel field is part of the received ICP cells so its information can be read by software from those cells However ICP cells are only received when the S...

Page 1178: ...Inverse Multiplexing for ATM IMA MPC8260 PowerQUICC II Family Reference Manual Rev 2 33 76 Freescale Semiconductor...

Page 1179: ...dard low cost PHY devices in system applications instead of PHYs that support UTOPIA bus devices A typical TC layer application requires the use of one SI TDM channel per TC block As shown in Figure 3...

Page 1180: ...neation state machine Payload descrambling using self synchronizing scrambler programmable by the user Coset removing programmable by the user Filtering idle unassigned cells programmable by the user...

Page 1181: ...ells transmitted Transmitted ATM cells Received ATM cells Maskable interrupt sent to the host when a counter expires Overrun Rx cell FIFO and underrun Tx cell FIFO condition produces maskable interrup...

Page 1182: ...performs a sequential bit by bit hunt for a correct HEC sequence While performing this hunt the cell delineation state machine is in HUNT state When a correct HEC is found the RCF locks on the particu...

Page 1183: ...CRC 8 calculation over the first four octets of the ATM cell header The RCF verifies the received HEC using the accumulation polynomial x8 x2 x 1 The coset polynomial x6 x4 x2 1 is added modulo 2 to...

Page 1184: ...Functions The transmit ATM cell functions block TCF performs the ATM cell payload scrambling and is responsible for the HEC generation and the idle cell generation The TCF scrambles programmable by t...

Page 1185: ...re required for some applications and must be supported Table 34 1 describes the signals required for operating the TC layer 34 4 TC Layer Programming Mode This section describes the TC layer specific...

Page 1186: ...data 4 RC Rx Coset Enable 0 XOR with 0xAA is done on received HEC 1 No XOR with 0xAA is done on received HEC 5 TC Tx Coset Enable 0 XOR with 0xAA is done on transmitted HEC 1 No XOR with 0xAA is done...

Page 1187: ...x data is transferred as soon as it is enabled 1 Tx data is transferred byte aligned to the Txsyn signal 13 IMA IMA mode 0 Rx is not in IMA 1 Rx is in IMA mode 14 SM Single mode 0 TC is not the only P...

Page 1188: ...terrupt is enabled only if TCMODE URE is set The idle cell header is 0x00000001 I 432 whose HEC is 0x52 The idle cell payload is 0x6A I 432 2 CDT Cell delineation toggled Set when the cell delineation...

Page 1189: ...it stands for an ORed event register of a TC block Once a bit is set it indicates that one or more event bits are set in the corresponding TC block event register Table 34 5 describes TCGER fields 34...

Page 1190: ...a cell is completed 34 4 3 3 Errored Cell Counter 1 8 TC_ECCx This cell counter is updated whenever a received errored cell cell with header error is discarded 34 4 3 4 Corrected Cell Counter 1 8 TC_...

Page 1191: ...leared This change then causes a TCER CDT interrupt to the host if enabled in the mask register TCMRx On the receive path the TC layer receives the bit stream via the SI and does the following 1 Attem...

Page 1192: ...required by the physical medium device PMD On PowerQUICC II there are two ATM transmit modes Users should refer to Section 30 2 1 5 Transmit External Rate and Internal Rate Modes for more details The...

Page 1193: ...plementation Example Figure 34 12 shows the PowerQUICC II connected to two PHY devices each containing four T1 framers The eight T1 bit streams are connected to the eight PowerQUICC II SI TDMs and rou...

Page 1194: ...Programming a T1 Application This section describes the configurations necessary to implement a T1 application using a single TC layer block Note that using two or more TCs requires FCC2 to work in M...

Page 1195: ...rogrammed as shown in Table 16 Table 34 9 Programming the CPM MUX for a TI Application Step 5 The TCx layer block should be configured using the TCMODEx and CDSMR1 registers as shown in Table 17 Note...

Page 1196: ...alize the serial interface registers and enable TDM in this case TDMa on SI1 as shown in Table 19 Table 34 11 Programming the SI RAM Rx or Tx for a T1 Application Init Values Description SI_RAM 00 0x0...

Page 1197: ...EE 802 3 frames to exist on the same LAN the length field must be unique from any type fields used in Ethernet This requirement limits the length of the data portion of the frame to 1 500 bytes and th...

Page 1198: ...egister GFMRx MODE selects Ethernet protocol that FCC performs the full set of IEEE 802 3 Ethernet CSMA CD media access control MAC and channel interface functions Figure 35 2 shows a block diagram of...

Page 1199: ...p Bit rates up to 100 Mbps Receives back to back frames Detection of receive frames that are too long Multibuffer data structure Supports 48 bit addresses in three modes Physical One 48 bit address re...

Page 1200: ...ng the PowerQUICC II to Ethernet Each FCC has 18 signals defined by the IEEE 802 3u standard for connecting to an Ethernet PHY The two management signals MDC and MDIO required by the MII should be imp...

Page 1201: ...carrier sense to become inactive at which point the controller determines if CRS remains negated for 16 serial clocks If so the transmission begins after an additional 8 serial clocks 96 bit times af...

Page 1202: ...which case frame reception continues normally unless the CAM specifically signals the frame to be rejected See Section 35 7 CAM Interface If an address is recognized the Ethernet controller fetches th...

Page 1203: ...5 7 CAM Interface The PowerQUICC II internal address recognition logic can be used in combination with an external CAM When using a CAM the FCC must be in promiscuous mode FPSMRx PRO 1 See Section 35...

Page 1204: ...Does not count frames not addressed to the station frames received in the out of buffers condition or frames with overrun errors 0x54 DISFC 2 Word Discard frame counter Incremented for discarded fram...

Page 1205: ...l address filter high low Used in the hash table function of the individual addressing mode The user can write zeros to these values after reset and before the Ethernet channel is enabled to disable a...

Page 1206: ...s than MAXD1 0xBC MAXD Hword Rx maximum DMA Internal usage 0xBE DMA_CNT Hword Rx DMA counter Temporary down counter used to track the frame length 0xC0 OCTC 2 Word RMON mode only The total number of o...

Page 1207: ...E0 P64C 2 Word RMON mode only The total number of packets including bad packets received that were 64 octets long excluding framing bits but including FCS octets 0xE4 P65C 2 Word RMON mode only The to...

Page 1208: ...smitter is disabled Note that the INIT TX AND RX PARAMETERS command can also be used to reset the transmit and receive parameters Table 35 4 Receive Commands Command Description ENTER HUNT MODE After...

Page 1209: ...ata including those in bad packets received on the network excluding framing bits but including FCS octets OCTC etherStatsPkts The total number of packets including bad packets broadcast packets and m...

Page 1210: ...tion 8 2 1 5 10BASE5 and Section 10 3 1 4 10BASE2 These documents define jabber as the condition where any packet exceeds 20 ms The allowed range to detect jabber is between 20 ms and 150 ms JBRC ethe...

Page 1211: ...cale Semiconductor 35 15 Check Address I G Address Individual Addr Match I G Broadcast Addr Broadcast Enabled T Receive Frame T Hash Search Use Group Table Hash Search Use Individual Table T Match T P...

Page 1212: ...lly accessed correctly That is the CPM attempts to access the CAM on the 60x bus but the 60x to local bus bridge logic detects the 60x bus transaction and forwards it to the CAM on the local bus 35 13...

Page 1213: ...he preamble sequence the jam pattern is sent after the sequence ends If a collision occurs within 64 byte times the process is retried The transmitter waits a random number of slot times A slot time i...

Page 1214: ...roller resumes transmission after receiving the RESTART TRANSMIT command Note that late collision parameters are defined in FPSMR LCW Table 35 7 Reception Errors Error Description Overrun error The Et...

Page 1215: ...ation when using this feature which allows the user to test the PowerQUICC II collision logic It causes the retry limit to be exceeded for each transmit frame 2 SBT Stop backoff timer 0 The backoff ti...

Page 1216: ...ess of its address A CAM can be used for address filtering when FSMR CAM is set 10 FCE Flow control enable 0 Flow control is not enabled 1 Flow control is enabled 11 RSH Receive short frames 0 Discard...

Page 1217: ...mmand is complete When the command is issued GRA is set as soon the transmitter finishes sending a frame in progress If no frame is in progress GRA is set immediately 9 RXC RX control A control frame...

Page 1218: ...Idle Stored in Rx Buffer RXD RX_DV Frame Received in Ethernet Time Line Idle TXD TX_EN Frame Transmitted by Ethernet COL TXB GRA TXB Line Idle Line Idle Stored in Tx Buffer Notes Ethernet FCCE Events...

Page 1219: ...rupt is generated after this buffer is used 1 FCCE RXB or FCCE RXF are set when this buffer is used by the Ethernet controller These two bits can cause interrupts if they are enabled 4 L Last in frame...

Page 1220: ...Broadcast address Valid only for the last buffer in a frame RxBD L 1 The received frame address is the broadcast address 9 MC Multicast address Valid only for the last buffer in a frame RxBD L 1 The r...

Page 1221: ...E F Receive BD 0 Status Length Pointer 0 0x0045 32 Bit Buffer Pointer 0 E F Receive BD 1 Status Length Pointer 1 XXXX 32 Bit Buffer Pointer E Receive BD 2 Status Length Pointer 1 XXXX 32 Bit Buffer Po...

Page 1222: ...incoming data into the first BD that TBASE points to in the table The number of TxBDs in this table is programmable and determined only by the W bit The TxBD table must contain more than one BD in Eth...

Page 1223: ...cates the number of retries required for this frame to be successfully sent If RC 0 the frame is sent correctly the first time If RC 15 and RET_LIM 15 in the parameter RAM 15 retries were needed If RC...

Page 1224: ...Fast Ethernet Controller MPC8260 PowerQUICC II Family Reference Manual Rev 2 35 28 Freescale Semiconductor...

Page 1225: ...The exact use and structure of this field depends upon the protocol using the frame Data is transmitted in the data field which can vary in length depending upon the protocol using the frame Layer 3 f...

Page 1226: ...osing flag In HDLC the lsb of each octet and the msb of the CRC are sent first Figure 36 1 shows a typical HDLC frame Figure 36 1 HDLC Framing Structure After the closing flag is sent the HDLC control...

Page 1227: ...field is checked against the recalculated value and written to the buffer The data length written to the last BD in the HDLC frame is the length of the entire frame This enables HDLC protocols that lo...

Page 1228: ...ed Note that the user should provide enough empty RxBDs to receive the number of frames specified in RFTHR 0x5C RFCNT Hword Received frames count A decrementing counter used to implement this feature...

Page 1229: ...flushed The TBPTR is not advanced no new BD is accessed and no new frames are sent for this channel The transmitter sends an abort sequence consisting of 0x7F if the command was given during frame tr...

Page 1230: ...nd the channel is enabled in the FCC mode register the channel is in receive enable mode and uses the first BD in the table The ENTER HUNT MODE command is generally used to force the HDLC receiver to...

Page 1231: ...ror and there will be no indication of error Abort Sequence The HDLC controller detects an abort sequence when seven or more consecutive ones are received When this error occurs and the HDLC controlle...

Page 1232: ...ther values of NOF are decremented by 1 when FSE is set This is useful in signaling system 7 applications 5 MFF Multiple frames in FIFO Setting MFF applies only when in RTS mode GFMRx RTSM 1 0 Normal...

Page 1233: ...ata and always before the next edge of the serial clock Note that at the end of the frame after the closing flag RTS negates a maximum of 5 CPM clocks after the active edge of TCLK 17 23 Reserved shou...

Page 1234: ...ss 1 Address 2 Control Byte Buffer CRC Byte 1 CRC Byte 2 Buffer Address 1 Address 2 Buffer Control Byte Empty 32 Bytes 32 Bytes 32 Bytes 32 Bytes Two Frames Received in HDLC Unexpected Abort Stored in...

Page 1235: ...RXB bit is not set after this buffer is used but RXF operation remains unaffected 1 FCCE RXB or FCCE RXF is set when the HDLC controller uses this buffer These two bits can cause interrupts if they a...

Page 1236: ...esented to the HDLC controller for transmission on an FCC channel by arranging it in buffers referenced by the channel TxBD table The HDLC controller confirms transmission or indicates errors using th...

Page 1237: ...BD that TBASE points to in the table The number of TxBDs in this table is determined only by the W bit and the overall space constraints of the dual port RAM 3 I Interrupt 0 No interrupt is generated...

Page 1238: ...quest Interrupts generated by the FCCE can be masked in the HDLC mask register FCCM which has the same bit format as FCCE If an FCCM bit 1 the corresponding interrupt in the event register is enabled...

Page 1239: ...of the last bit of the closing flag 13 BSY Busy condition A frame is received and discarded due to a lack of buffers 14 TXB Transmit buffer Enabled by setting TxBD I A buffer is sent on the HDLC chann...

Page 1240: ...RTS Frame Transmitted by HDLC CTS TXB CT CT Line Idle Line Idle Stored in Tx Buffer Notes HDLC FCCE Events 1 RXB event assumes receive buffers are 6 bytes each 2 The second IDL event occurs after 15 o...

Page 1241: ...s set as soon as an HDLC flag 0x7E is received on the line Once FG is set it remains set at least 8 bit times while the next 8 bits of input data are examined If another flag occurs FG stays set for a...

Page 1242: ...FCC HDLC Controller MPC8260 PowerQUICC II Family Reference Manual Rev 2 36 18 Freescale Semiconductor...

Page 1243: ...FMRx TTx enables the transparent transmitter setting GFMRx TRx enables the transparent receiver Both bits must be set for full duplex transparent operation If only one bit is set the other half of the...

Page 1244: ...DMA channel transmit synchronization must be established before data can be sent Similarly once the FCC receiver is enabled for transparent operation in the GFMR and the RxBD is made empty for the FCC...

Page 1245: ...bsequent data bits are sent accurately Similarly if CTS is in pulse mode GFMR CTSP 1 only the first frame is affected If CTS is not in pulse mode GFMR CTSP 0 every frame is affected separately Note th...

Page 1246: ...irst Bit of Frame Data Output is CLKx Input TXD Output is RXD Input RTS Output is CD Input or CRC TxBD L 1 Causes Negation of RTS CD Lost Condition Terminates Reception of Frame PowerQUICC II A PowerQ...

Page 1247: ...t The transmitter and receiver sections use the same clock which is derived from the SPI baud rate generator in master mode and generated externally in slave mode During an SPI transfer data is sent a...

Page 1248: ...a shared SPI signal is driven by the PowerQUICC II or an external SPI device The SPI master in slave out SPIMISO signal acts as an input for master devices and as an output for slave devices Converse...

Page 1249: ...O PDPAR DD19 0 Figure 38 2 Single Master Multi Slave Configuration To start exchanging data the core writes the data to be sent into a buffer configures a TxBD with TxBD R set and configures one or m...

Page 1250: ...shifts data out from SPIMISO and in through SPIMOSI A maskable interrupt is issued when a full buffer finishes receiving and sending or after an error The SPI uses successive RxBDs in the table to co...

Page 1251: ...SELOUT1 SPI 2 SPIMISO SPIMOSI PowerQUICC II SELOUT1 SPISEL SPICLK SELOUT3 SELOUT2 SPIMISO SPIMOSI SPI 1 SELOUT0 SPISEL SPICLK SELOUT3 SELOUT2 SPI 0 Notes All signals are open drain For a system with...

Page 1252: ...n 1 Loopback mode The transmitter output is internally connected to the receiver input The receiver and transmitter operate normally except that received data is ignored 2 CI Clock invert Inverts SPI...

Page 1253: ...Section 40 2 Port Registers 8 11 LEN Character length in bits per character If the character length is not greater than a byte every byte in memory holds LEN 1 valid bits If the character length is gr...

Page 1254: ...y image msb ghij_klmn__opqr_stuv lsb Example 1 with LEN 4 data size 5 the following data is selected msb xxxj_klmn__xxxr_stuv lsb with REV 0 the data string image is msb j_klmn__r_stuv lsb the order o...

Page 1255: ..._klmn last 38 4 2 SPI Event Mask Registers SPIE SPIM The SPI event register SPIE generates interrupts and reports events recognized by the SPI When an event is recognized the SPI sets the correspondin...

Page 1256: ...ed They should be changed only when the SPI is inactive Table 38 5 shows the memory map of the SPI parameter RAM 6 TXB Tx buffer Set when the Tx data of the last character in the buffer is written to...

Page 1257: ...les back to back The change takes effect when the CP moves control to the next RxBD To guarantee the exact RxBD on which the change occurs change MRBLR only while the SPI receiver is disabled MRBLR sh...

Page 1258: ...ccess bit 0 Disable memory snooping 1 Enable memory snooping 3 4 BO Byte ordering Set BO to select the required byte ordering for the buffer If BO is changed on the fly it takes effect at the beginnin...

Page 1259: ...s and control bits The CP updates the status bits after the buffer is sent or received The half word at offset 2 contains the data length in bytes that is sent or received For an RxBD this is the numb...

Page 1260: ...the buffer when the SPI is configured as a slave and SPISEL is negated indicating that reception stopped The core should write RxBD bits before the SPI is enabled The format of an RxBD is shown in Fi...

Page 1261: ...reception from an SPI slave into one buffer for autoscanning of a serial A D peripheral with no core overhead 7 13 Reserved should be cleared 14 OV Overrun Set when a receiver overrun occurs during re...

Page 1262: ...he CP receives incoming data using the BD pointed to by TBASE top of the table The number of BDs in this table is determined only by the W bit and overall space constraints of the dual port RAM 3 I In...

Page 1263: ...al purpose I O signal as shown in Figure 38 2 1 Enable SPIMISO SPIMOSI SPICLK and SPISEL 2 In address 0x89FC assign a pointer to the SPI parameter RAM 3 Assuming one RxBD at the beginning of the dual...

Page 1264: ...riggering an out of buffers error If the master sends more than 16 bytes the RxBD is closed full and an out of buffers error occurs after the 17th byte is received 38 10 Handling Interrupts in the SPI...

Page 1265: ...k which is derived from the I2 C BRG when in master mode and generated externally when in slave mode Wait states are inserted during a data transfer if SCL is held low by a slave device In the middle...

Page 1266: ...lock BRGCLK which is generated from the CPM clock see Section 10 8 System Clock Control Register SCCR SDA and SCL are bidirectional signals connected to a positive supply voltage through an external p...

Page 1267: ...aster or slave mode for the controller using the I2 C command register I2COM M S Set the master s start bit I2COM STR to begin a transfer setting a slave s I2COM STR activates the slave to wait for a...

Page 1268: ...tion for master write requests The master I2C controller simply issues a write request directed to its own address programmed in I2ADD The master s receiver monitors the transmission and reads the tra...

Page 1269: ...software considerations must be made A PowerQUICC II I2C controller attempting a master read request could simultaneously be targeted for an external master write slave read Both operations trigger th...

Page 1270: ...ransferred first Note Clearing REVD is strongly recommended to ensure consistent bit ordering across devices 3 GCD General call disable Determines whether the receiver acknowledges a general call addr...

Page 1271: ...interrupt Unmasked I2CER bits must be cleared before the CP clears internal interrupt requests Figure 39 9 shows both registers 0 6 7 Field SAD Reset Undefined R W R W Addr 0x0x11864 Figure 39 7 I2 C...

Page 1272: ...irst character is received but discarded because no Rx buffer is available 6 TXB Tx buffer Set when the Tx data of the last character in the buffer is written to the Tx FIFO Two character times must e...

Page 1273: ...the I2 C Furthermore do not configure BD tables of the I2 C to overlap any other active controller s parameter RAM RBASE and TBASE should be divisible by eight 0x02 TBASE Hword 0x04 RFCR Byte Rx Tx fu...

Page 1274: ...accessed 0x20 TBPTR Hword TxBD pointer Points to the next descriptor that the transmitter transfers data from when it is in an idle state or to the current descriptor during frame transmission After...

Page 1275: ...1 Big endian 1x Munged little endian 5 TC2 Transfer code 2 Contains the transfer code value of TC 2 used during this SDMA channel memory access TC 0 1 is driven with a 0b11 to identify this SDMA chann...

Page 1276: ...For a TxBD this is the number of octets the CP should transmit from its buffer Normally this value should be greater than zero The CP never modifies this field The word at offset 4 points to the begin...

Page 1277: ...uld be cleared 2 W Wrap last BD in table 0 Not the last BD in the RxBD table 1 Last BD in the RxBD table After this buffer is used the CP receives incoming data using the BD pointed to by RBASE top of...

Page 1278: ...s set when the buffer is serviced If enabled an interrupt occurs 4 L Last 0 This buffer does not contain the last character of the message 1 This buffer contains the last character of the message The...

Page 1279: ...significant flexibility many dedicated peripheral functions are multiplexed onto the ports The functions are grouped to maximize the pins usefulness in the greatest number of PowerQUICC II applicatio...

Page 1280: ...d If a port pin is configured as an input data written to PDATx is still stored in the output latch but is prevented from reaching the port pin In this case when PDATx is read the state of the port pi...

Page 1281: ...PDATC only Figure 40 2 Port Data Registers PDATA PDATD 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field DR01 DR11 DR21 DR31 DR4 DR5 DR6 DR7 DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15 Reset 0000_0000_0000_0000 R...

Page 1282: ...21 22 23 24 25 26 27 28 29 30 31 Field DD16 DD17 DD18 DD19 DD20 DD21 DD22 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31 Reset 0000_0000_0000_0000 R W R W Addr 0x10D06 PPARA 0x10D26 PPARB 0x10D46 PPARC...

Page 1283: ...O13 SO14 SO15 Reset 0000_0000_0000_0000 R W R W Addr 0x0x10D08 PSORA 0x0x10D28 PSORB 0x0x10D48 PSORC 0x0x10D68 PSORD 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field SO16 SO17 SO18 SO19 SO20 SO21...

Page 1284: ...IN1 Default Input IN2 To DED IN1 To DED IN2 From DED OUT2 PDATx Read 0 1 0 1 PPAR PSOR PDIR PPAR PSOR PDIR Open Drain Control EN PODR 0 Latch From DED OUT1 PSOR 1 0 1 PDATx Write To from internal bus...

Page 1285: ...n input data written to PDATx is still stored in the output latch but is prevented from reaching the port pin In this case when PDATx is read the state of the port pin is read 40 4 2 Dedicated Pins Wh...

Page 1286: ...nput PDIRA 1 Output PDIRA 0 Input or Inout if Specified Defaul t Input PA31 FCC1 TxEnb1 UTOPIA master FCC1 TxEnb1 UTOPIA slave GND FCC1 COL MII GND PA30 FCC1 TxClav1 UTOPIA slave FCC1 TxClav1 UTOPIA m...

Page 1287: ...FCC1 TxD 4 1 UTOPIA 8 FCC1 TxD 12 1 UTOPIA 16 FCC1 TxD 3 MII HDLC nibble PA20 FCC1 TxD 5 1 UTOPIA 8 FCC1 TxD 13 1 UTOPIA 16 FCC1 TxD 2 MII HDLC nibble PA19 FCC1 TxD 6 UTOPIA 8 FCC1 TxD 14 UTOPIA 16 FC...

Page 1288: ...nibble GND PA14 FCC1 RxD 4 1 UTOPIA 8 FCC1 RxD 12 1 UTOPIA 16 FCC1 RxD 3 MII HDLC nibble GND PA13 FCC1 RxD 3 1 UTOPIA 8 FCC1 RxD 11 1 UTOPIA 16 GND MSNUM 2 2 PA12 FCC1 RxD 2 1 UTOPIA 8 FCC1 RxD 10 1...

Page 1289: ...Y master CLK19 GND IDMA4 DACK TDM_A2 L1RXD 1 Nibble GND PA2 FCC2 TxAddr 0 1 MPHY master CLK20 GND IDMA3 DACK PA1 FCC2 TxAddr 1 1 MPHY master SCC1 REJECT VDD IDMA3 DONE Inout VDD PA0 SCC1 RSTRT FCC2 Tx...

Page 1290: ...B27 FCC2 TxD 0 1 UTOPIA 8 FCC2 COL MII GND TDM_C2 L1TXD Inout GND PB26 FCC2 TxD 1 1 UTOPIA 8 FCC2 CRS MII GND TDM_C2 L1RXD Inout GND PB25 FCC2 TxD 4 1 UTOPIA 8 FCC2 TxD 3 MII HDLC nibble TDM_A1 L1TXD...

Page 1291: ...CRS MII GND SCC2 TXD TDM_C1 L1RSYNC primary option by PD26 PB11 FCC2 TxD 0 1 UTOPIA 8 FCC3 RxD 3 MII HDLC nibble GND TDM_D1 L1TXD Inout primary option by PD25 PB10 FCC2 TxD 1 1 UTOPIA 8 FCC3 RxD 2 MII...

Page 1292: ...Table 40 7 Port C Dedicated Pin Assignment PPARC 1 PIN Pin Function PSORC 0 PSORC 1 PDIRC 1 Output PDIRC 0 Input Defaul t Input PDIRC 1 Output PDIRC 0 Input or Inout if Specified Defaul t Input PC31 B...

Page 1293: ...HY master FCC1 TxAddr 0 1 3 MPHY slave FCC2 TxAddr 4 MPHY slave GND PC14 SCC1 CD SCC1 RENA Ethernet GND FCC1 RxAddr 0 1 MPHY master FCC1 RxAddr 0 1 3 MPHY slave FCC2 RxAddr 4 1 MPHY slave GND PC13 TDM...

Page 1294: ...M_C1 L1CLKO FCC1 CD GND FCC1 RxAddr 2 1 MPHY master multiplexed polling FCC1 RxAddr 2 1 3 MPHY slave multiplexed polling FCC1 RxClav11 3 MPHY master direct polling FCC2 RxAddr 2 1 MPHY slave multiplex...

Page 1295: ...Addr 3 1 2 MPHY master multiplexed polling FCC2 RxAddr 4 1 MPHY master multiplexed polling FCC1 RxAddr 3 1 3 MPHY slave multiplexed polling FCC1 RxClav21 3 MPHY master direct polling FCC2 RxAddr 1 1 M...

Page 1296: ...iplexed polling FCC2 RxAddr 3 1 MPHY master multiplexed polling FCC1 RxAddr 4 1 3 MPHY slave multiplexed polling FCC1 RxClav31 3 MPHY master direct polling FCC2 RxAddr 0 1 MPHY slave multiplexed polli...

Page 1297: ...ter multiplexed polling FCC1 TxAddr 3 1 3 MPHY slave multiplexed polling FCC1 TxClav21 3 MPHY master direct polling FCC2 TxAddr 1 1 MPHY slave multiplexed polling GND PD6 FCC1 TxD 4 1 UTOPIA 16 IDMA1...

Page 1298: ...determine which edges cause interrupts 4 Write the corresponding SIMR mask register bit with a 1 to allow interrupts to be generated to the core 5 The pin value can be read at any time using PDATC NO...

Page 1299: ...60 are SPRs except for the machine state register MSR described in Table A 3 Table A 1 User Level PowerPC Registers non SPRs Description Name Comments Access Level Serialize Access General purpose reg...

Page 1300: ...d Sync relative to load store operations 19 00000 10011 DAR See the Programming Environments Manual Write Full sync Read Sync relative to load store operations 22 00000 10110 DEC See the Programming E...

Page 1301: ...ual 978 11110 10010 HASH1 See the MPC603e RISC Microprocessor User s Manual 979 11110 10011 HASH2 See the MPC603e RISC Microprocessor User s Manual 980 11110 10100 IMISS See the MPC603e RISC Microproc...

Page 1302: ...Register Quick Reference Guide MPC8260 PowerQUICC II Family Reference Manual Rev 2 A 4 Freescale Semiconductor...

Page 1303: ...e and figure numbers B 1 Document Errata The following list includes the document errata Section Page Changes 4 3 1 1 4 19 In Table 4 4 the reserved field should be bits 8 13 as shown in Figure 4 10 a...

Page 1304: ...not used or cannot initiate global transactions Assertion must occur at least one cycle following AACK for the current transaction otherwise assertion may occur at any time during the assertion of DBB...

Page 1305: ...h the following Both the PCI configuration and memory mapped internal registers of the PCI bridge are intrinsically little endian and are described using classic bit numbering that is the lowest memor...

Page 1306: ...description of BRx V Note If BRx has been selected as the SDRAM controller and the valid bit has been set BRx 31 1 the SDRAM controller must be invalidated by doing the following 1 Disable the SDRAM...

Page 1307: ...scription in Section 14 3 7 RISC Controller Configuration Register RCCR 5 Emergency from FCCs MCCs and SCCs 6 IDMA 1 4 emulation option 2 1 7 33 Same relative priority 34 IDMA 1 4 emulation option 3 1...

Page 1308: ...ther or not an IDMA is in progress Therefore whenever the IDMA s DREQ is active all CPM peripherals with a priority lower than the IDMA do not receive service The IDMA priority can be configured via R...

Page 1309: ...19 4 to Internal use Must be cleared before every START_IDMA command 19 8 5 19 25 Add the following note after the first paragraph The CPM always clears the valid V bit in an IDMA buffer descriptor b...

Page 1310: ...also contained in this document as an errata for Section 30 13 2 The description is not shown in the manual 30 10 1 3 30 43 Add GBL at bit 2 in Figure 30 23 and Table 30 14 as shown in the following 3...

Page 1311: ...to Section 30 10 7 UNI Statistics Table to the end of RxPRTY s description 30 12 2 30 89 Add the following to the beginning of the section In UTOPIA slave mode single or multiple PHY cells are transf...

Page 1312: ...18 TPRI Transmitter priority Used to adjust the default priority of the FCC transmitter It is strongly recommended to set TPRI when in multi PHY mode or in single PHY mode if the maximal bit rate eit...

Page 1313: ...ture allows the user to change the IMA APC behavior upon TRL request When enabled the TRL request will pass a programmable number of cells to the Tx queue of the links in an IMA group This can be used...

Page 1314: ...terations Enable 0 APC is not split TRL completes round robin distribution of cells 1 APC split both TRL and non TRL requests distribute cells to the transmit queues 0 1 2 3 4 5 6 7 Field TSTF TIMSTF...

Page 1315: ...the CPM before issuing a new CP command Refer to Section 20 4 Command Set 0 1 2 3 5 6 7 8 9 10 11 12 13 14 15 OFFSET 0 V W TQU TQO DSL LS DCBO LDS GDS IFSD IFSW OFFSET 2 L G NUM 9 DSL DCB synchroniza...

Page 1316: ...flipped such that it is logically inverted with respect to the ILRCNTL ADD_NEW bit It is recommended however that software after GDS failure and when restarting the GDS process changes all of the lin...

Page 1317: ...ect It should refer to note 2 available only when the primary option for this function is not used and not note 3 0 7 DIV Division ratio 0 7 Specifies the divide ratio of the BRG divider in the I2 C c...

Page 1318: ...Reference Manual Rev 1 Errata MPC8260 PowerQUICC II Family Reference Manual Rev 2 B 16 Freescale Semiconductor...

Page 1319: ...m asynchronous exception is used interchangeably with the word interrupt Atomic access A bus access that attempts to be part of a read write operation to the same address uninterrupted by any other ac...

Page 1320: ...esponding to the most recent value written to memory or to another processor s cache Cache flush An operation that removes from a cache any data from a specified address range This operation ensures t...

Page 1321: ...tion to either a physical memory address or an I O address Exception A condition encountered by the processor that requires special supervisor level processing Exception handler A software routine tha...

Page 1322: ...e defined only for 64 bit implementations are considered to be illegal instructions For 64 bit implementations instructions that are defined only for 32 bit implementations are considered to be illega...

Page 1323: ...hat has been granted control or mastership of the bus Memory access ordering The specific order in which the processor performs load and store memory accesses and the order in which those accesses com...

Page 1324: ...ture such as an instruction a register or an exception that is defined by the PowerPC architecture but not required to be implemented Out of order An aspect of an operation that allows it to be perfor...

Page 1325: ...ns starting at an address divisible by 16 R rA The rA instruction field is used to specify a GPR to be used as a source or destination rB The rB instruction field is used to specify a GPR to be used a...

Page 1326: ...on Set v To write a nonzero value to a bit or bit field the opposite of clear The term set may also be used to generally describe the updating of a bit or bit field Set n A subdivision of a cache Cach...

Page 1327: ...struction set user level registers data types floating point memory conventions and exception model as seen by user programs and the memory and programming models User mode The unprivileged operating...

Page 1328: ...policy in which processor write cycles are directly written only to the cache External memory is updated only indirectly for example when a modified cache block is cast out to make room for newer data...

Page 1329: ...nded transfer mode 8 19 extended write cycle data bus contents 8 20 little endian mode 8 32 LSDMR register 11 23 lwarx stwcx support 8 32 MEI protocol 8 30 memory coherency 8 30 no pipeline mode 8 24...

Page 1330: ...view 32 20 sublayer structure 32 2 switching example 32 3 transmitter 32 5 AAL2 Tx data structures 32 8 CPS buffer structure 32 15 CPS Tx queue descriptor 32 13 SSSAR transmit buffer descriptor 32 19...

Page 1331: ...0 80 UTOPIA interface 30 84 VCI filtering 30 39 VCI VPI address lookup 30 13 VC level address compression tables VCLT 30 17 VP level address compression table VPLT 30 16 B Baud rate generator BRG BRGC...

Page 1332: ...tion timing 11 53 chip select machine 11 51 signals 11 74 write enable deassertion timing 11 54 Clocks basic power structure 10 11 clock divider 10 5 clock unit 10 1 external clock inputs 10 1 general...

Page 1333: ...5 30 49 ATM channel code 30 41 overview 30 41 raw cell queue 30 18 RCT entry format 30 43 registers 30 87 RxBD 30 71 RxBD extension 30 76 SRTS generation using external logic 30 94 transmit connection...

Page 1334: ...ission 36 2 overview 36 1 parameter RAM 36 3 programming model 36 5 receive commands 36 6 reception errors 36 6 RxBD 36 9 transmission errors 36 6 transmit commands 36 5 TxBD 36 12 overview block diag...

Page 1335: ...HDLC parameters channel specific 28 5 initialization 28 47 INTMSK 28 15 MCCE 28 37 MCCFx 28 33 MCCM 28 37 parameters for transparent operation 28 11 RSTATE 28 10 RxBD 28 43 TSTATE 28 7 TxBD 28 45 over...

Page 1336: ...monitor function 4 2 masking interrupt sources 4 13 MCC relative priority 4 12 periodic interrupt timer PIT 4 5 periodic interrupt timer PIT function 4 2 pin multiplexing 4 49 PISCR 4 46 PITC 4 46 PI...

Page 1337: ...cations controllers FCCs Fast Ethernet mode address recognition 35 14 block diagram 35 2 CAM interface 35 7 collision handling 35 17 connecting to the MPC8260 35 4 error handling 35 17 FCCE 35 20 FCCM...

Page 1338: ...lers MCCs 28 1 processor core 2 3 RISC timer tables 14 22 serial communications controllers SCCs AppleTalk mode 26 2 BISYNC mode 23 2 general list 20 2 HDLC mode 22 1 transparent mode 24 1 UART mode 2...

Page 1339: ...ock diagram 39 1 BRGCLK 39 2 clocking and pin functions 39 2 commands 39 11 features list 39 2 loopback testing 39 4 master read slave write 39 4 master write slave read 39 3 multi master consideratio...

Page 1340: ...ELL_TMP_BASE 33 26 group tables 33 29 group receive control IGRCNTL 33 38 group receive state IGRSTATE 33 39 group receive table entry 33 36 group transmit state IGTSTATE 33 31 ICP cell templates 33 3...

Page 1341: ...plementation 13 5 L L_TESCR1 local bus transfer error status and control register 1 4 42 L_TESCR2 local bus transfer error status and control register 2 4 43 L_TESCRx local bus error status and contro...

Page 1342: ...41 overview 11 38 precharge to activate interval 11 39 refresh recovery interval RFRC 11 42 pipeline accesses 11 36 power on initialization 11 35 read write transactions supported 11 46 refresh 11 47...

Page 1343: ...mode 28 13 28 15 channel extra parameters 28 28 commands 28 34 data structure organization 28 2 exceptions 28 36 features list 28 1 global parameters 28 4 28 15 HDLC parameters channel specific 28 5 i...

Page 1344: ...egister 9 53 device ID register 9 47 general purpose local access base address registers GPLABARx 9 54 Hot Swap control status register 9 61 initializing the PCI configuration registers 9 64 PCI bus a...

Page 1345: ...tbound FIFO queue port register OFQPR 9 78 outbound message interrupt mask register OMIMR 9 79 outbound message interrupt status register OMISR 9 78 queue base address register QBAR 9 84 inbound FIFOs...

Page 1346: ...gisters AppleTalk mode GSMR 26 3 PSMR 26 4 TODR 26 4 ATM controller FCCE 30 90 FCCM 30 90 FPSMR FCC protocol specific mode register 30 88 FTIRRx 30 92 B 10 GFMR register 30 88 BISYNC mode BDLE 23 8 BS...

Page 1347: ...56 bus function 9 58 bus interrupt line 9 56 bus interrupt pin 9 57 bus latency timer 9 52 bus MAX LAT 9 58 bus MIN GNT 9 57 bus programming interface register 9 50 configuration registers 9 45 devic...

Page 1348: ...and register 9 47 PCI bus internal memory mapped registers bass address PIMMRBAR 9 53 PCI bus status register 9 48 reader type 9 52 revision ID register 9 49 subclass code register 9 50 subsystem devi...

Page 1349: ...TER 18 7 TGCR 18 3 TMR 18 5 TRR 18 6 TODR AppleTalk mode 26 4 overview 20 10 TOSEQ 21 9 transparent mode PSMR 24 8 SCCE 24 11 SCCM 24 11 SCCS 24 12 UART mode DSR 21 10 PSMR 21 12 SCCE 21 19 SCCM 21 1...

Page 1350: ...pleTalk mode connecting to AppleTalk 26 2 operating LocalTalk frame 26 1 overview 26 1 programming example 22 22 26 4 programming the controller 26 3 BISYNC mode commands 23 4 control character recogn...

Page 1351: ...configuration 14 3 Serial interface SI enabling connections 15 7 features 15 3 GCI support 15 30 IDL bus implementation programming the IDL 15 29 IDL interface support 15 25 overview 15 4 programming...

Page 1352: ...T 8 12 TCn 8 12 TSIZn 8 12 TTn 8 9 byte select signals 11 75 chip select signals 11 74 clock signals 10 5 general purpose signals 11 76 IDMA emulation DACKx 19 13 DONEx 19 15 DREQx 19 13 memory contro...

Page 1353: ...4 25 signal multiplexing 4 49 SIMR_H 4 22 4 23 SIPNR_H 4 21 SIPNR_L 4 21 SIPRR 4 18 SIUMCR 4 33 SIVEC 4 24 software watchdog timer 4 6 SWR 4 7 SWSR 4 38 SYPCR 4 37 system protection 4 2 TESCR1 4 38 T...

Page 1354: ...operation 37 2 frame reception 24 2 frame transmission 24 2 inherent synchronization 24 5 in line synchronization 24 5 overview 24 1 programming example 24 12 RxBD 24 8 serial management controllers S...

Page 1355: ...quests 11 67 hierarchical bus interface example 11 101 implementation differences with SDRAM machine and GPCM 11 6 loop control 11 76 memory access requests 11 66 memory system interface example 11 81...

Page 1356: ...MPC8260 PowerQUICC II Family Reference Manual Rev 2 Index 28 Freescale Semiconductor U U Index...

Page 1357: ...Module Overview 14 Serial Interface with Time Slot Assigner 15 CPM Multiplexing 16 Baud Rate Generators BRGs 17 Timers 18 SDMA Channels and IDMA Emulation 19 Serial Communications Controllers SCCs 20...

Page 1358: ...sor Module Overview 15 Serial Interface with Time Slot Assigner 16 CPM Multiplexing 17 Baud Rate Generators BRGs 18 Timers 19 SDMA Channels and IDMA Emulation 20 Serial Communications Controllers SCCs...

Page 1359: ...Controller 36 FCC Transparent Controller 37 Serial Peripheral Interface SPI 38 I2 C Controller 39 Parallel I O Ports 40 Register Quick Reference Guide A Reference Manual Rev 1 Errata B Glossary of Te...

Page 1360: ...DLC Controller 37 FCC Transparent Controller 38 Serial Peripheral Interface SPI 39 I2 C Controller 40 Parallel I O Ports A Register Quick Reference Guide B Reference Manual Rev 1 Errata GLO Glossary o...

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