Freescale Semiconductor MPC8250, Family Reference Manual

Page: 384 / 1360

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-78 Freescale Semiconductor
9.12.3.4.2 Outbound FIFO Queue Port Register (OFQPR)
OFQPR is used by PCI masters to access outbound messages in local memory. Local processor does not
have access to this port. OFQPR should be accessed only from the PCI bus. OFQPR is described in
Figure 9-74 and Table 9-59 .
Figure 9-74. Outbound FIFO Queue Port Register (OFQPR)
9.12.3.4.3 Outbound Message Interrupt Status Register (OMISR)
OMISR contains the interrupt status of the I
2
O, door bell, and outbound message registers. A PCI device
acknowledges the outbound message interrupt by writing a 1 to the appropriate status bit: OMISR[OM1I]
or OMISR[OM0I]. This clears both the interrupt and the corresponding status bit. The local processor
provokes an outbound message interrupt by writing to either of the two outbound message registers:
OMR0 or OMR1. OMISR should be accessed only from the PCI bus IFQPR should be accessed only from
the PCI bus.
Table 9-58. IFQPR Field Descriptions
Bits Name Description
31–0 IFQP Inbound FIFO queue port. Reading this register will return the MFA from inbound free
list FIFO. Writing to this register will post the MFA to the inbound post list FIFO.
31 16
Field OFQP
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10446
15 0
Field OFQP
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x10444
Table 9-59. OFQPR Field Descriptions
Bits Name Description
31–0 OFQP Outbound FIFO queue port. Reading this register will return the MFA from outbound
post list FIFO. Writing this register will post the MFA to the outbound free list FIFO.