Freescale Semiconductor MPC8250, Family Reference Manual

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SCC BISYNC Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 23-3
23.3 SCC BISYNC Channel Frame Reception
Although the receiver is designed to work with almost no core intervention, the user can intervene on a
per-byte basis if necessary. The receiver performs CRC16, longitudinal (LRC) or vertical redundancy
(VRC) checking, sync stripping in normal mode, DLE-sync stripping, stripping of the first DLE in
DLE-DLE pairs in transparent mode, and control character recognition. Control characters are discussed
in
Section 23.6, “SCC BISYNC Control Character Recognition.”
When enabled, the receiver enters hunt mode where the data is shifted into the receiver shift register one
bit at a time and the contents of the shift register are compared to the contents of DSR[SYN1, SYN2]. If
the two are unequal, the next bit is shifted in and the comparison is repeated. When registers match, hunt
mode is terminated and character assembly begins. The controller is character-synchronized and performs
SYNC stripping and message reception. It reverts to hunt mode when it receives an
ENTER HUNT MODE
command, an error condition, or an appropriate control character.
When receiving data, the controller updates the CR bit in the BD for each byte transferred. When the buffer
is full, the controller clears the E bit in the BD and generates an interrupt if the I bit in the BD is set. If
incoming data exceeds the buffer length, the controller fetches the next BD; if E is zero, reception
continues to its buffer.
When a BCS is received, it is checked and written to the buffer. The BISYNC controller sets the last bit,
writes the message status bits into the BD, clears the E bit, and then generates a maskable interrupt,
indicating that a block of data was received and is in memory. The BCS calculations do not include SYNCs
(in nontransparent mode) or DLE-SYNC pairs (in transparent mode).
Note that GSMR_H[RFW] should be set for an 8-bit-wide receive FIFO for the BISYNC receiver. See
Section 20.1.1, “The General SCC Mode Registers (GSMR1–GSMR4).”
23.4 SCC BISYNC Parameter RAM
For BISYNC mode, the protocol-specific area of the SCC parameter RAM is mapped as in Table 23-1 .
Table 23-1. SCC BISYNC Parameter RAM Memory Map
Offset
1
Name Width Description
0x30 — Word Reserved
0x34 CRCC Word CRC constant temp value.
0x38 PRCRC Hword Preset receiver/transmitter CRC16/LRC. These values should be preset to all
ones or zeros, depending on the BCS used.
0x3A PTCRC Hword
0x3C PAREC Hword Receive parity error counter. This 16-bit (modulo 2
16
) counter maintained by the
CP counts parity errors on receive if the parity feature of BISYNC is enabled.
Initialize PAREC while the channel is disabled.
0x3E BSYNC Hword BISYNC SYNC register. Contains the value of the SYNC to be sent as the second
byte of a DLE–SYNC pair in an underrun condition and stripped from incoming
data on receive once the receiver synchronizes to the data using the DSR and
SYN1–SYN2 pair. See
Section 23.7, “BISYNC SYNC Register (BSYNC) .”