Instruction Model
e200z3 Power Architecture Core Reference Manual, Rev. 2
3-6
Freescale Semiconductor
3.10
e200z3-Specific Instructions
The e200z3 core implements the following instructions that are not defined by the Book E architecture:
•
The EIS-defined integer select (isel) APU consists of the isel instruction, described in
Section 3.10.1, “Integer Select APU.”
•
The Return from Debug Interrupt instruction (rfdi) is defined by the Freescale Book E debug APU.
This instruction is described in
•
The wait instruction implements a wait for interrupt function and is described in
. This instruction is implemented in the e200z335 only.
•
The signal processing extension (SPE) APU provides a set of 64-bit SIMD instructions. These are
listed in
Section 3.10.5, “SPE APU Instructions,”
and described in the EREF.
•
The embedded vector and scalar single-precision floating-point APUs are listed along with
supporting instructions in
Section 3.10.6, “Embedded Vector and Scalar Single-Precision
Floating-Point APU Instructions.”
These instructions are described in detail in the EREF.
3.10.1
Integer Select APU
The integer select APU defines the Integer Select (isel) instruction, which provides a means to select one
of two registers and place the result in a destination register under the control of a predicate value supplied
by a bit in the condition register. isel can be used to eliminate branches in software and in many cases
improve performance; it can also increase program execution time determinism by eliminating the need to
predict the target and direction of the branches replaced by the integer select function.
The isel instruction form and definition are described in the EREF
3.10.2
Debug APU
The e200z3 implements the Freescale Book E debug APU to support the ability to handle the debug
interrupt as an additional interrupt level. To support this interrupt level, the Return from Debug Interrupt
instruction (rfdi) is defined as part of the debug APU, along with a pair of save/restore registers, DSRR0,
and DSRR1.
When the debug APU is enabled (HID0[DAPUEN] = 1), rfdi provides a way to return from a debug
interrupt. See
Section 2.13.1, “Hardware Implementation-Dependent Register 0 (HID0),”
for more
information about enabling the debug APU.
The instruction form and definition is provided in the EREF.
3.10.3
Wait APU (e200z335 only)
The wait instruction allows software to cease all synchronous activity, waiting for an asynchronous
interrupt to occur. The instruction can be used to cease processor activity in both user and supervisor
modes. Asynchronous interrupts which will cause the waiting state to be exited if enabled are critical input,
external input, machine check input. Nonmaskable interrupts will also cause the waiting state to be exited.
The instruction form and definition is provided in the EREF.
