Instruction Pipeline and Execution Timing
e200z3 Power Architecture Core Reference Manual, Rev. 2
6-4
Freescale Semiconductor
instruction is a load/store instruction, and the latter instruction is using the previous load data for its
effective address (EA) calculation.
Loads, when free of the above EA calculation dependency, execute with a maximum throughput of one
per cycle and one-cycle latency. Store data can be fed forward from an immediately preceding load with
no stall.
6.3
Instruction Pipeline
The four-stage processor pipeline consists of stages for instruction fetch (IFETCH), instruction decode
(DECODE), execution (EXECUTE), and result writeback (WB). For memory operations, the EA
generation occurs in the decode stage, while the memory access occurs in the execute stage.
The processor also contains an instruction prefetch buffer to allow buffering of instructions prior to the
decode stage. Instructions proceed from this buffer to the instruction decode stage by entering the
instruction decode register IR.
Figure 6-2. Pipeline Diagram
6.3.1
Description of Pipeline Stages
The fetch pipeline stages retrieve instructions from the memory system and determine where the next
instruction fetch is performed. Up to two instructions every cycle are sent from memory to the instruction
buffers.
Table 6-1. Pipeline Stages
Stage
Description
IFETCH1
Instruction fetch from memory
DECODE/EA
Instruction decode/register read/operand forwarding/EA calculation
EXECUTE/MEM
Instruction execution/memory access
WB
Write back to registers
IFetch
Decode
Execute
Writeback
I1
I2
IFetch
Decode/EA calc/Drive Address
Memory access/Drive Data Back
L1
L2
L1
L2
L1
L2
Writeback
L1
L2
Simple Instruction
Load/Store Instruction
I1
I2
I1
I2
I1
I2
