Debug Support
e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor
9-19
Although OCMD is updated during the Update-IR TAP controller state, the corresponding resource is
accessed in the DR scan sequence of the TAP controller, and as such, the Update-DR state must be
transitioned through for an access to occur. In addition, the Update-DR state must also be transitioned
through in order for the single-step and/or exit functionality to be performed, even though the command
appears to have no data resource requirement associated with it.
describes OCMD fields.
.
0
1
2
3
9
Field
R/W
GO
EX
RS
Reset
0b10_0000_0010 on assertion of
j_trst_b or m_por or while in test-logic-reset state
Figure 9-6. OnCE Command Register (OCMD)
Table 9-7. OCMD Field Descriptions
Bits Name
Description
0
R/W
Read/Write. Specifies the direction of data transfer.
0 Write the data associated with the command into the register specified by RS
1 Read the data contained in the register specified by RS
Note: R/W is generally ignored for read-only or write-only registers, although the PC FIFO pointer is only
guaranteed to be updated when R/W = 1. In addition, it is ignored for all bypass operations. When performing
writes, most registers are sampled in the Capture-DR state into a 32-bit shift register and subsequently shifted
out on
j_tdo
during the first 32 clocks of Shift-DR.
1
GO
Go. If the GO bit is set, the chip executes the instruction which resides in the IR register in the CPUSCR. To
execute the instruction, the processor leaves debug mode, executes the instruction, and, if the EX bit is cleared,
returns to debug mode immediately after executing the instruction. The processor goes on to normal operation if
the EX bit is set, and no other debug request source is set. The GO command is executed only if the operation is
a read/write to CPUSCR or a read/write to no register selecte. Otherwise the GO bit is ignored. The processor
leaves debug mode after the TAP controller Update-DR state is entered.
On a Go+NoExit operation, returning to debug mode is treated as a debug event; thus, exceptions such as
machine checks and interrupts may take priority and prevent execution of the intended instruction. Debug
firmware should mask these exceptions as appropriate. OSR[ERR] indicates such an occurrence.
0 Inactive (no action taken)
1 Execute instruction in IR