Fluke NetDAQ 2640A, Service Manual

Page: 82 / 260

NetDAQ
Service Manual
2-40
Integrate 2-69.
The integrate state is when the input voltage is actually connected to the integrator.
PREF and NREF are each switched off and on 10 to 20 times during this state and DREF
is still off, INT is on, AZ is off, and the CMP signal is switching off and on. The primary
signal is pin 7 of A3U19, which looks approximately like a triangular wave with 51.2
µ
s
slope when the input voltage is zero. The triangular wave is very irregular at other
voltages, moving on an upward or downward slope and reversing direction within the
integrate time period. The actual behavior is determined by the algorithm in the FPGA.
This tests the CMP signal at defined times spaced 51.2
µ
s apart. If the CMP signal is
turned off, then NREF is turned on. PREF and NREF are never on at the same time
during integrate. First, the existing reference is turned off and a 1-count (1.6 us) period is
entered where only the input signal is integrated. Next, a reference of a polarity such as
to keep the total number of NREF pulses so far equal to the number of PREF pulses is
turned on for 1-count (1.6
µ
s).
Finally, the reference with a polarity determined by the comparator (CMP) test at the
very first of the interval is turned on for the remaining 30 counts (48
µ
s) of the interval.
The beginning first interval is only 16 counts instead of 32 counts. The last state is 35
counts to allow for completing the PREF and NREF pulse count equalization. There are
8 normal intervals of 32 counts. The purpose is to bound the waveform to prevent
amplifier saturation, prevent charge injection from being a variable with waveform
changes and prevent logic signals themselves from injecting unwanted signals into the
summing node.
The integrate state is the primary measuring interval, and during this time the FPGA
accumulates counts of how long PREF and NREF have been applied. The count is
completed during deintegrate. Typical integrator output waveforms for different inputs
are shown in Figure 2-11, Figure 2-12, and Figure 2-13.
0.5V/Div.
0V dc
125
µ
s/Div.
Figure 2-11. Integrator Output Waveform for Input Near 0