Fluke NetDAQ 2640A, Service Manual

Page: 70 / 260

NetDAQ
Service Manual
2-28
Table 2-5. Front Panel Switch Scanning
Interface Signal States or Key Sensed
Step SWR6 SWR5 SWR4 SWR3 SWR2 SWR1
1 A2S17 A2S10 A2S12 A2S18 A2S13
2 A2S11 0
3 0 Z
4 A2S14 A2S15 A2S16 0 Z Z
5 n/a n/a 0 Z Z Z
6 A2S21 0 Z Z Z Z
A2Sn indicates switch closure sensed.
0 indicates strobe driven to logic 0.
Z indicates high impedance input state ignored.
Display 2-51.
The custom vacuum-fluorescent display (A2DS1) consists of a filament, 11 grids
(numbered 0 through 10 from right to left on the display), and up to 14 anodes under
each grid. The anodes make up the digits and annunciators for their respective area of the
display. The grids are positioned between the filament and the anodes.
A 5.4V ac signal, biased at a -24V dc level, drives the filament. When a grid is driven to
+5V dc, the electrons from the filament are accelerated toward the anodes that are under
that grid. Anodes under that grid that are also driven to +5V dc are illuminated, but the
anodes that are driven to -30V dc are not. Grids are driven to +5V dc one at a time,
sequencing from GRID(10) to GRID(0) (left to right, as the display is viewed.)
Beeper Drive Circuit 2-52.
The Beeper Drive circuit drives the speaker (A2LS1) to provide an audible response to a
button press. A valid entry yields a short beep; an incorrect entry yields a longer beep.
The circuitry consists of a dual four-bit binary counter (A2U4) and a NAND gate
(A2U6) used as an inverter. One four-bit free-running counter (A2U4) divides the
1.024-MHz clock signal (E) from the FPGA (DSCLK) by 2 to generate the 512-kHz
clock (CLK1) used by the Display Controller. This counter also divides the 1.024-MHz
clock by 16, generating the 64-kHz clock that drives the second four-bit binary counter
(A2U4).
The second four-bit counter is controlled by an open-drain output on the Display
Controller (A2U1-17) and pull-down resistor A2R1. When the beeper (A2LS1) is off,
A2U1-17 is pulled to ground by A2R1. This signal is then inverted by A2U6, with
A2U6-6 driving the CLR input high to hold the four-bit counter reset. Output A2U4-8 of
the four-bit counter drives the parallel combination of the beeper (A2LS1) and A2R10 to
ground to keep the beeper silent. When commanded by the Microprocessor, the Display
Controller drives A2U1-17 high, enabling the beeper and driving the CLR input of the
four-bit counter (A2U4-12) low. A 4-kHz square wave then appears at counter output
A2U4-8 and across the parallel combination of A2LS1 and A2R10, causing the beeper to
resonate.