Fluke NetDAQ 2640A, Service Manual

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Theory of Operation
Detailed Circuit Description
2
2-17
The RAM* signal (A1U1-127) enables access to the Static RAM (A1U20, A1U30,
A1U34, or A1U35). There are two banks of static RAM. The SRAM decoding circuit
(A1U14, A1U15, A1R125, and A1R126) selects one of the two banks. The RAM1*
signal selects one bank (A1U20 and A1U30) and RAM2* selects the other bank (A1U34
and A1U35). A1R125 is installed for 128Kx8 SRAMs, or A1R126 is installed for
512Kx8 SRAMs. The I/O* and ENET* signals go to the I/O Decoder (A1U29), which
decodes small areas of address space for I/O devices like the FPGA, the Real-Time
Clock, and the Ethernet Interface.
There are no wait states for accesses to FLSH* and SRAM*, but two wait states are used
for any access to I/O*. Each wait state adds approximately 65 nanoseconds to the length
of a memory read or write cycle. The Ethernet Interface (A1U32) handles wait state
timing for any accesses to ENET*. When the Microprocessor is starting up (also referred
to as "booting"), the address decoding maps the address space as shown in Table 2-2.
Table 2-2. Booting Microprocessor Memory Map
Hexadecimal Address Device Selected
000000 - 07FFFF Flash (A1U21)
200000 - 27FFFF SRAM (A1U20, A1U30, A1U34, and A1U35)
400000 - 401000 Microprocessor Internal
500000 - 50000F Ethernet Interface (A1U32)
600000 - 60007F FPGA Configuration (A1U31)
600080 - 6000FF Real-Time Clock (A1U11)
Just before beginning execution of the instrument code, the address decoding is changed
to map the address space as shown in Table 2-3. This change switches the positions of
Flash Memory and Static RAM within the address space of the Microprocessor. Note
that the Flash Memory is duplicated at two address ranges. When the instrument code
begins executing, it runs out of the address range beginning at 088000 Hex.
Table 2-3. Instrument Microprocessor Memory Map
Hexadecimal Address Device Selected
000000 - 07FFFF SRAM (A1U20, A1U30, A1U34, and A1U35)
080000 - 87FFFF Flash (A1U21)
088000 - 8FFFFF Flash (A1U21)
400000 - 401000 Microprocessor Internal
500000 - 50000F Ethernet Interface (A1U32)
600000 - 600007 FPGA Control / Status (A1U31)
600008 - 60000F Alarm Outputs (A1U31)
600010 - 600017 Digital Outputs (A1U31)
600018 - 60001F (Read Only) Digital Inputs (A1U31)
600020 - 600027 (Read Only) Keyboard Input (A1U31)
600028 - 60002F (Read Only) Totalizer LSB Input (A1U31)
600030 - 600037 (Read Only) Totalizer MSB Input (A1U31)
600080 - 6000FF Real-Time Clock (A1U11)