Fluke 9132A, Service Manual

Page: 22 / 92

Fa
9132A Service
All input port signals
(IDO through ID15)
can be
read
by
the Pod processor.
U98 and U46 are data buffers between
the
input ports and the microproces-
sor data lines. These ports are enabled during an input port select
(INPORTSEL-) and
a read.
The inputs from the ROM Modules pass through a non-inverting buffer
(U45). PROMTYPEI, 2,
and 3 are
signals
from ROM Module
1
that
determine the
type
of ROM Module. Headers contained
on
the ROM
Module designate the size of the ROM Module
(ie.,
24-, 28-, or 32-pin).
ROMA4SEL-, ROM3SEL-, and ROM2SEL- are
used
for self test modes
only. ROMISEL-,
an output from ROM Module
1,
indicating that all of the
ROM Module
1
chip selects and
output enables are active.
ROMISEL-
is
monitored
at
U45 to determine if
an error exists.
ROMIPRESENT-, ROM2PRESENT-, ROM3PRESENT-, and ROM4PRE-
SENT-
on
U12 indicate how many ROM Modules are connected to the
Pod.
PM-PRESENT- indicates whether
the
Personality Module is present. Re-
set latch (RESET-LAT)
is an
output from
the
Personality Module that
shows the module has
seen
a reset at the
UUT microprocessor. Clack fail
(CLK-FAIL) comes from a circuit
on
page
6
of the Main Board schematics
that detects activity on
the
UUT clock
line. Compare equal (COMPAREQ-)
is a non-clock output from
the
address comparator
(used
for self test pur-
poses here).
The DELAY ROMADDR
lines on
Ul3
are the delayed versions of the
ROM addresses. These addresses return status during certain accesses.
MAINSTAT and ABORT on U48
are
active high versions of the handshake
lines from
the
Mainframe.
Sync
fuse
sense
(SYNCFUSESENSE) and
ROM fuse sense (ROMxFUSESENSE) indicate whether
the
fuses on the
Sync Module and ROM Modules are
good.
Pod data 0 through
7 on
U11
are
input Pod data from the Mainframe.
The ROMxPWRFAIL lines show whether power
has
failed
on
the indicated
ROM Modules. Self test (SFTST-) indicates that a ROM Module is
plugged into the self test socket.
The self test
sync
present (STSYNC-
PRSNT-) line indicates that a
Sync
Module is plugged into the self test
socket. BANKAAVAIL
and
BANKBAVAIL monitor the progress of the
ERAM bank
swaps.
Main
Board Address
RAM
and Sync
Module
Interface
2-8.
The Main Board Address RAM and
Sync
Module interface circuitry are
shown
on
page 6 of
the
Main Board schematic (Figure 5-1).
The address RAMs (ARAM),
U61
and U62,
are
8K
x 8
static RAMs
divided into banks of 2K
x 16.
The ARAM
is
used
as
a “mini
logic
analyzer,” to
latch a stream of addresses from ROM Module
1
and store it
16 bits
at a time.
Once the address stream is latched, the Pod processor
can access the results using either byte-wide or word-wide reads.
The delayed address (DELAY ROMADDR)
can pass through
U87
and U97
to the ARAM-DATA bus. When the
address RAM
is
armed (by enabling
the output port bit ARAM-EN
at
U56), both U87 and U97 are always turned