Fluke 9132A, Service Manual

Page: 21 / 92

9132A Service
through the
first line of Exclusive OR gates
in the
comparator (explained
earlier in this section).
UB6
controls various types of
outputs.
Enable abort (EN-ABORT) allows
the
Pod
to
abort either from COMPAREQ- or from the Mainframe ABORT.
Arm select (ARMSEL)
selects the mode of arming
the
sync counter
latch,
Arm enable (ARMEN) enables
the
entire
sync
counter circuitry. ROM
1
don’t care (ROMIDC-) goes to
the address comparator
on page
2 of the
Main Board schematics to determine if ROMISEL-
is to be
ignored.
REARM
arms
the CLKLATCH
circuitry.
RUNUUT
request
(RUNUUTREQ) requests the Pod
to go into RUNUUT mode when this
signal
is latched.
Sync
enable
(SYNCEN)
controls
the sync
output line to
the Mainframe
(in
cases where
a sync
signal must be generated internally
but is not sent
to
the Mainframe).
The Pod
sync
control lines (PSYNCCTL1-4) on U57 control the
sync
counter circuitry. Self test control (SLFTST-CNTL-32, SLFTST-CNTL-30,
and SLFTST-CNTL-28)
on U57
control the self test relays (K1, K2,
and
K3)
that supply
power
to
the ROM Modules.
The
ROM1PINXDC-
lines
on
U75,
U67
,
and US7 pin 12
go to the address
comparator
on page
2
of
the
Main Board schematics
and
determine if
the
comparator
bit
is to be
passed or ignored.
All of the outputs of
U59 (PIN29EN-, PIN29POL-, etc.) go to the ROM
Modules. These
lines tell the ROM Module
which
pins of the ROM are
active chip enable
(CE)
or output enable (OE),
and designate the polarity of
the pins.
U43, H1,
and Z1 are used for debug purposes
and are not
normally installed.
U84 controls PODSTAT-
and
PODINT-
to
the Mainframe. Pod data
out
(PODDATAQUT)
is an
enable
to the
data buffer that drives
the
data
lines
in the Pod cable to
the Mainframe.
:
Pod data
(PODDATAQ through PODDATA7)
on
U22 is
the
data sent
to the
Mainframe.
Reset polarity (RESETPOL)
on US5
controls whether the UUT reset line
is
driven
high
or low.
The reset request (REQRESET) line enables the reset
overdrive. Force
sync
(FRCSYNC) is used internally to force the
sync
pulse. Swap select (SWAP-SELECT) chooses the mode to clock the bank
swaps (either the next BCYCLECLK- or SCl1).
Force bank
A
(FRCBANKA) and
force bank
B (FRCBANKB) force bank
swaps.
PLZACCBNKA/-B
requests the timed bank
swap.
Power present
(PWRFAIL/PRSENT) informs
the
Mainframe whether there
is a
power
fail
(high). If the
power fail line
is in an invalid or tri-state level, the Mainframe
considers the Pod not present.
ARAM-SEL-0 and ARAM-SEL-1
on
U56 select one of the four different
banks of address
RAM.
ROM
test
enable (ROM-TST-EN) allows the
Pod
to dynamically switch in and out of RUNUUT
on
a sync pulse. Overdrive
channel
3
(OVDRVCH3) allows
the Sync
Module
to
overdrive one of
the
UUT lines
(such as a
HOLD
line) during
sync
counter activity. ARAM-EN
arms the address RAM
to
allow
it to capture the address trace.