Fluke 9132A, Service Manual

Page: 18 / 92

9132A Service
In some
modes
the
CLKLATCH output from U21B clocks the
Ul3
latch
(U13 is shown on
page
5 of the Main Board schematics). This
latch
receives
the low eight addresses from ROM Module
1.
When CLKLATCH goes
true, U13 is
latched and the lower 4 bits of UUT ROM address latched into
U13 allow
the
Pod to receive status information from the UUT.
A small circuit composed of U9
and
U28D creates the overdrive reset
(OVDRV-RESET)
signal.
The inputs to this circuit are reset request
(REQRESET), a line that is
written to or controlled by the processor,
ABORT,
a
line that comes from the Mainframe, and enable abort
(EN-
ABORT),
a
line from
an output port on
U86
(UB6 is
shown of page
5
of
the
Main Board schematics). This circuit allows three methods of
overdriving
the UUT. If the
REQRESET
line
from
the
Pod goes high, the overdrive reset
(OVDRV-RESET) line forces the Pod to overdrive the reset of the UUT. If
the
EN-ABORT
line
to the circuit is active, either the ABORT line from the
Mainframe or
the
clock latch from
U21B (preset
as
a comparator for a
breakpoint) can be used
to
overdrive the
UUT.
CLKLATCH is cleared either
by
a RESET- (from the
Mainframe or power-
up
reset)
or by the
output port signal
REARM.
The bank switch lines from U4
and
U24 allow
the
Pod to
switch
between
two banks of emulation RAM. The ERAM bank switch circuitry allows the
Pod
to
switch cleanly between banks of RAM without causing metastable or
timing problems.
Two signals called force bank A (FRCBANKA) and
force bank B
(FRCBANKB) enter the bank switch circuit at
Ul6. (FRCBANKA and
FRCBANKB are output port
bits
controlled
by
the Pod processor.) If both
FRCBANKA
and
FRCBANKB
are true,
both banks of ERAM are available
to the Pod
and, consequently, not available to
the ROM Modules. If only
one of the banks is forced, the forced bank is available to the Pod processor,
but
the
other bank
is
available
to
the ROM Modules.
Using force bank to
switch
banks
is nonsynchronous and can cause runtime
problems with the UUT processor. To make a
clean swap between banks,
the PLZACCBNKA/-B line
is
used to switch banks when BCYCLECLK-
is
cycled.
The AND/OR gate (U19) that the
swap select (SWAP-SELECT) line
enters allows two different ways to
initiate
a swap.
When SWAP-SELECT
is set in one mode, the next
true
BCYCLECLK- that clocks U27B swaps
the banks. When SWAP-SELECT is in the
other mode, SC11 (the sync
counter output) is
used for swap select when the Pod goes into RUNUUT
mode.
This type of
swap
has two accesses. U27B gets swapped on
the
first clock
and is then set and
ready.
(At
that
time,
when U27B is swapped
and U27A is
not,
neither bank
is
available to the Pod processor. Whichever
bank was available to the ROM Module is still available.)
On the next
clock cycle,
when
BCYCLECLK- clocks pin 3
of U27A, the actual swap
occurs.
‘This
swap occurs regardless of which mode
was
selected; it is
the
BCYCLECLK- after the first bank
is swapped that actually causes the bank
swap.
This prevents metastable conditions caused by the delay between
the two flip-flops
(U27)
that could produce
an
indeterminate output
state.
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