Fluke 9132A, Service Manual

Page: 16 / 92

9132A Service
The heart of
the
Pod
is a
68000 microprocessor
(U92).
The processor is
reset
by the
RESET-
line.
This line
is
produced either
by
the PODRESET-
line from
the
Mainframe or
by
the power-up reset RC network. The BERR-,
BR-, and BG-
signals
are
not used during operation. The interrupt
lines
(IPLx) are all tied high through 4.7K-ohm resistors. An 8-MHz oscillator
(U91)
clocks
the
processor.
The main address decoding
is
achieved
by an
HCT138 (U40). U40 divides
the address space into
several
64K segments. Each of
the
lines that select
the segments begins with a specific letter that identifies its destination. If
the line begins with “K”,
such as KROMSEL-, the K
refers to kernel,
as
in
kernel ROM select or kernel RAM
select.
“P” refers to personality,
such
as
PMROMSEL- or Personality Module ROM
select.
“A” refers
to ad-
dress, such
as
ARAM-SEL or address RAM
select. “E” refers to emula-
tion, such as ERAMSEL- or emulation RAM
select. U40 also has lines
for
output port select (QUTPORTSEL-) and input port select INPORTSEL-).
The port selects from U40
are
divided
by
three ACT138s (U83
and U73 are
output port decoders,
and U3 is an
input port decoder) into the output port or
input port selects.
Each output port select
is
divided into high
and
low
bytes, and can be
written
to
either
as a
byte or a word
(i.e.,
U83 and U73
can be
selected
at
the same time or either one can be selected individually).
The outputs from
U83 correspond to the high data lines, and the outputs
from
U73 correspond
to the
low data lines. Extra decoding for U83
and
U73
is provided from the UDS- and
LDS- lines from
the
microprocessor, which
are gated
to write lower
(WL-) and
write upper
(WU-).
WL-
and
WU-
are
active during a write cycle if LDS-
and
UDS- are active.
A
word write
forces both data strobes active, which in tum activates WL-
and
WU-
at
the same
time.
ERAMSEL-
on
pin
11
of U40
is
further broken down into ERAMASEL- and
ERAMBSEL- through
U28.
These signals
are
the bank selects for the
emulation RAM (ERAM). The state of
AlS5
determines which bank of
RAM
is
selected
(A15
low
=
bank
A, A15 high = bank B).
The kernel ROM consists of two
32K x 8
CMOS ROMs (U90
and
U89).
The kernel RAM consists of two
32K x 8 static
RAMs
(U95
and U88).
Self test enable
is
determined
by A23 and
interrupt acknowledge.
If
any
access that is not
an
interrupt acknowledge occurs while A23
is high,
it
is
counted
as a
self test access. These accesses pulse self test latch enable
(ST-LE), the output of U16 pin 13.
If the access
is a read, a self test output
enable (ST-OE-) occurs. These
signals
disable
all
internal accesses and
access only the self test ports when A23
is
high.
Main
Board Sync Generation
Timing
2-4.
The Main Board
sync
generation timing circuitry is
shown
on page
2
of the
Main Board schematic (Figure
5-1).
A
Main Board
sync
generation timing
block diagram
is
shown
in Figure
2-2.
A 16-bit address comparator looks
at
the address lines of ROM Module
1.
(The
various signals coming onto the main Pod board are, for example,
labeled
ROM1IPIN28 or ROMIPIN3.)
These
are
the address lines of the
boot ROM coming from the ROM Module. Other types of inputs entering
2-3