Fluke 9132A, Service Manual

Page: 20 / 92

9132A Service
Main
Board Emulation
RAM
Control
2-6.
The Main Board Emulation RAM control circuitry
is
shown
on
page
4
of
the
Main Board schematic (Figure
5-1).
The Pod processor can
switch
control of read
and
write to either bank of
emulation RAM
on
the RAM Module(s).
In
normal mode, the Pod
processor can read
and write to one bank of emulation RAM while the other
bank
is being used
by
the ROM
Modules. The bank available lines
(BANKAAVAIL and BANKBAVAIL) select
the mode of the different
muxes
(U65,
U72, U69, U81, U74, U71, U78,
and U80). Depending
on
the
state of BANKAAVAIL
and
BANKBAVAIL, either the address lines from
the Pod processor or the ROM Module
1
address bus (ROMADDR) are
used
by
the emulation
RAM.
Two of the bank available muxes ICs
(U65 and
U74) perform a four-to-one
mux
(as
opposed to two-to-one
by the
others). Emulation RAM address
12 and emulation RAM address
11
require the
four-to-one mux because
some ROMs, such
as
the 2364,
switch pin
numbers of address lines
All
and A12.
The positions of RAM address
12 and
11
allow software control of
the placement of
A11 and
A12 on the
ROM.
Two other lines, called AI2ENABLE- and A11ENABLE-, are also sent to
U65 and U74.
Since some ROM types
use
only
10 address
lines,
A12ENABLE- and A11ENABLE- disable address
lines
All
and A12 from
the RAM Module
and
hold them
in a stable
condition while ROM Module
1
is not driving them.
Two latches
(U68
and U93) delay the ROM address
lines, allowing more
hold time for address
traces.
The lines are latched
by
an active
BCYCLECLK-. The address
is
latched
at the
end of the cycle and held. The
latches allow delayed clocking of the address
RAM
with no penalty since
the Pod
holds
the addresses
on
the outputs (i.e, DELAY ROMADDR)
until
the next ROM
access.
Any time the BCYCLECLK- is active low,
the
latches are transparent and the addresses pass straight through the
latches. Once the BCYCLECLK- goes
high,
U68 and U93 latch and hold the
last address until the next access.
Main
Board Input/Output Devices 2-7.
The Main Board input/output device circuitry is shown on
page
5
of the Main
Board schematic (Figure
5-1).
Two data buffers (U102 and U101) pass the data from the
Pod data
bus
to
the output data bus. The buffer outputs drive
the inputs to
all
of the Pod’s
latched output ports.
All output ports
on
the output data bus are
latched when the proper clock is
received. The clocking signal
is an
output port select (i.e., OUT2-, OUT4-,
etc.).
Each
of
the
ports can be written to as
a pair or singly, depending on
the selected mode (selected
as
either
a
word or byte write). Most of the
ports are cleared on
a reset or power-up reset and all the
outputs
go low.
The ROMIPINXPOL outputs from U85, U54, and pin
12
of U86 control the
polarity of the ROM Module
1
address
bus signals that are allowed to pass
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