Table 4-106 CMN_CCIX_CTRL Register bit assignments (continued)
Bits
Name
Type
Function
[24]
CXLA_CXSCLK _QREQ
RW
QREQn of CXLA CXSCLK control Q
channel at CXS interface side.
This bit maintains its reset value while the
CCIX subsystem is operating. It is only used
to complete Q-channel clock down handshake
when the CCIX subsystem, CCIX PCIe
controller, needs reset while the main part of
CMN
‑
600 is running. This is useful for CCIX
subsystem error clearance.
Reset value
0b1
.
[23:20] -
-
Reserved.
[19]
CXLA_PWR_QDENY
RO
QDENY of CXLA power control Q channel at
CXS interface side.
[18]
CXLA_PWR_QACCEPT
RO
QACCEPTN of CXLA power control Q
channel at CXS interface side.
[17]
CXLA_PWR_QACTIVE
RO
QACTIVE of CXLA power control Q channel
at CXS interface side.
[16]
CXLA_PWR_QREQ
RW
QREQn of CXLA power control Q channel at
CXS interface side.
This bit maintains its reset value while the
CCIX subsystem is operating. It is only used
to complete Q-channel power down
handshakes when the CCIX subsystem, CCIX
PCIe controller, needs reset while the main
part of CMN
‑
600 is running. This is useful for
CCIX subsystem error clearance.
Reset value
0b1
.
[15:0]
PCIE_BUS_NUM
RW
The PCIe ID{BUS_NUM[15:8],
DEVICE_NUM[7:3],
FUNCTION_NUM[2:0]} used for CMN
‑
600
to form its PCIe header.
When the CCIX is configured as RP, this field
must be set to
0x0
.
When the CCIX is configured as EP, the SCP
reads the End Point Bus and Device Number
Register of CCIX enabled PCIe controller and
set the value accordingly.
Interrupt
ccix_bus_device_change_irq
indicates a change of value in the controller.
4.5.76
STM_CTRL Register
The STM_CTRL Register characteristics are:
Purpose
Non-secure guaranteed access control.
4 Programmers model
4.5 Serial Configuration Control registers
101489_0000_02_en
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