S1R72105 Technical Manual
22
EPSON
Rev.1.0
7.3.12 Reset (Reset) R/W
Resets internal LSI. Each block is reset by writing HIGH to the corresponding bit.
Has the same effect as hard reset. Automatically returns to LOW.
Address
Register Name
Bit Symbol
Description
0Dh
Reset
7: 0
Reserved
6:
0
Reserved
5:
0
Reserved
4:
0
Reserved
3:
0
Reserved
2: PORT
Port Block Soft Reset
1: SCSI
SCSI Block Soft Reset
0: USB
USB Block Soft Reset
7.3.13 Port DMA Control (PortDMACtrl) R/W
Performs transfer operation of the port DMA.
Address
Register Name
Bit Symbol
Description
10h
PortDMACtrl
7: DMAmode1
DMA mode1
6: DMAmode0
DMA mode0
5:
0
Reserved
4:
0
Reserved
3:
0
Reserved
2:
0
Reserved
1: S_FIFO
SCSI FIFO Control
0: DTGO
DMA Transfer Go
BIT7-6 DMA mode1-0
Sets the DMA transfer mode.
mode1 mode0
Transfer
mode
0
0
Performs DMA transfer between the port and USB
0
1
Performs DMA transfer between the port and SCSI
1
0
Performs DMA transfer between SCSI and USB
1
1
Reserve (Setting disabled)
BIT1 SCSI FIFO Control
Concurrent setting of this bit and DTGO to HIGH does not cause DMA transfer by hardware. Instead, the CPU
transfers while monitoring the state of SCSI-FIFO (31-32H). The CPU must read or write data from or into
SCSI-FIFO according to the FULL/EMPTY status of SCSI-FIFO. Alternatively, data may be written into
SCSI-FIFO first to write HIGH into this bit and DTGO and to control, using the remaining data and FULL/EMPTY.
However, the CPU must not access FIFO in the direction opposite to transfer.
This bit is valid only in mode1:0 = 0:1 or 1:0. So use it when only SCSI needs to be transferred.
BIT0 DMA Transfer Go
Starts DMA transfer. The target transfer is specified by mode1:0 BIT.
The direction of transfer is automatically determined from the OUTxIN BIT set in each endpoint for USB or from the
command issued for SCSI
