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S1R72105 Technical Manual

Rev.1.0

EPSON

8.4.2.6 Initiator Asynchronous Data-out Timing (Data output)

Symbol Specification Min.

Typ.

Max.

Unit

223

XSREQ

↓

- XSACK

↓

- ns

224

XSDB valid - XSACK

↓

100

- - ns

225

XSREQ

↑

- XSACK

↑

226

XSACK

↑

- XSDB invalid

- ns

XSDB0-7,P

XSREQ

XSACK

224

226

223

225

Summary of Contents for S1R72105

Page 1: ...Technical Manual SCSI Interface Controller S1R72105 MF1530 01 ...

Page 2: ...reover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exch...

Page 3: ... 2 directions 0F Tape reel FRONT 0G TCP BT 4 directions 0H TCP BD 4 directions 0J TCP SL 2 directions 0K TCP SR 2 directions 0L Tape reel LEFT 0M TCP ST 2 directions 0N TCP SD 2 directions 0P TCP ST 4 directions 0Q TCP SD 4 directions 0R Tape reel RIGHT 99 Specs not fixed Specifications Shape F QFP Model number Model name R Exclusive use controller Peripheral Product classification S1 Semiconducto...

Page 4: ...tatWindow_0 R W 18 7 3 4 Interrupt Status Window 1 IntStatWindow_1 R W 19 7 3 5 Main Interrupt Enable MainIntEnb R W 19 7 3 6 EPr Interrupt Enable EPrIntEnb R W 19 7 3 7 Interrupt Enable Window 0 IntEnbWindow_0 R W 20 7 3 8 Interrupt Enable Window 1 IntEnbWindow_1 R W 20 7 3 9 Interrupt Index IntIndex R W 20 7 3 10 System Control SystemCtrl R W 21 7 3 11 USB Common USBCommon R W 21 7 3 12 Reset Re...

Page 5: ...Interrupt Enable EP r IntEnb R W 40 7 5 Detailed Description of Set Values of USBIndex Register 41 7 5 1 List of Registers Showing USBWindow Register 8 bytes Corresponding to Set Values of USBIndex Register 17h 41 7 5 2 Description of Registers by Set Value of USBIndex 42 7 5 2 1 USB Address USBAddress R W 42 7 5 2 2 EP0 Config 1 EP0Config_1 R W 42 7 5 2 3 EP0 In Transaction Control EP0InControl R...

Page 6: ...a in Timing Data input 74 8 4 2 8 Initiator Synchronous Data out Timing Data output 75 8 4 2 9 Initiator Synchronous Data in Timing Data input 76 8 4 2 10 Target Asynchronous Data in Timing Data output 77 8 4 2 11 Target Asynchronous Data out Timing Data input 78 8 4 2 12 Target Synchronous Data in Timing Data output 79 8 4 2 13 Target Synchronous Data out Timing Data input 80 8 4 3 Port Interface...

Page 7: ...d driver Active negation I O mounted USB Interface Compatible with full speed mode 12Mbps transfer Compatible with control transfer by endpoint 0 and bulk and interrupt transfers by three individual endpoints Split of the built in SRAM 256 bytes is programmable by user definition In addition to two way endpoint 0 a maximum of three endpoints can be set PORT Interface General purpose 8 16 bit selec...

Page 8: ...ol Synchronous transfer SCAM control XSRST XSDP XSREQ XSATN XSIO XSCD XSMSG XSSEL XSD7 0 XPUENB XSACK CPU interface section Timing control Interrupt control Data MPX DMA control section Start up stop control AD5 0 XCS XRD Phase control USB1 1 interface FIFO 256Byte Serial Interface Engine Transfer control ENDPOINTs control XUSBOE VBUS DP DM Internal register DB7 0 XWR XRESET TEST Bus control Clock...

Page 9: ... 81 45 PD2 5 HVDD 82 44 HVDD XSDBP 83 43 PD13 4 VSS 84 42 PD1 3 XSDB7 85 41 PD14 2 HVDD 86 40 PD0 1 XSDB6 87 39 PD15 0 VSS 88 38 VSS XSDB5 89 37 PDREQ HVDD 90 36 XPWR XSDB4 91 35 XPRD VSS 92 34 XPDACK XSDB3 93 33 HVDD HVDD 94 32 XRESET XSDB2 95 31 XCS VSS 96 30 XINTU XSDB1 97 29 XINTS HVDD 98 28 XRD XSDB0 99 27 XWR VSS 100 26 LVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 L...

Page 10: ... 48mA 66 XSIO I Ood SCSI I O signal Drive capability 48mA USB interface related matters 5 2 DM I O USB data port 3 DP I O USB data port Configure to pull up to 3 3V by a 1 5kΩ resistor externally The register can be controlled by XPUENB 5 XPUENB Ood Control signal connecting a 1 5kΩ pull up resistor to DP pin Ood VBUS 5V and HIGH EnPullUp USBCommon_b1 brings about LOW output Drive capability 6mA 6...

Page 11: ...nal 9 TESTEN Ipd Pin for testing connected to LOW GND usually 63 CLKSEL I Input clock and PLL operation selection HIGH LVDD Generates clock SCSI_40MHz USB_48MHz in internal PLL 20MHz oscillation in OSCIN OUT or input 20MHz 3 3V to OSCIN EXCLK is connected to LOW GND or HIGH LVDD LOW GND PLL stop power down external clock in operation 40MHz oscillation in OSCIN OUT or input 40MHz 3 3V to OSCIN Inpu...

Page 12: ...according to the timing specified by the PDREQ XPDACK signals 4 The port allows selection of bit width betweem 8 and 16 5 The port interface allows selection between the master and slave function toward PDREQ XPDACK XPRD XPWR direction 6 4 DMA Control Circuit This block controls the transfer between the DMA port and FIFO in the SCSI block and FIFO in the USB block It has the following functions 1 ...

Page 13: ...e oscillation circuit by using the PLL circuit The block diagram around the oscillation section is shown below The IC enables easy setup of an oscillation circuit by connecting a crystal vibrator and feedback resistor For characteristics of the crystal vibrator contact us separately It allows oscillation of 20MHz by means of the oscillation circuit mentioned above In this case 40MHz and 48MHz requ...

Page 14: ... from the OSCIN pin PLL is used When an oscillator circuit 40MHz is used When a 40 MHz clock of 3 3V level is input from the OSCIN pin PLL is not used Oscillation input clock 20MHz 40MHz CLKSEL LVDD GND EXCLK LVDD or GND Input 48MHz 3 3V PLL circuit specifications Ta 0 to 70 C LVDD 3 3V 0 3V Item Specifications Lock up time Within 1ms after oscillation was stabilized Jitter Within 1ns ...

Page 15: ...tEnbWindow_1 08h Interrupt Index IntIndex 09h System Control SystemCtrl 0Ah USB Common USBCommon 0Bh Reserved 0Ch Reserved 0Dh Reset Reset 0Eh Reserved 0Fh Reserved 10h Port DMA Control PortDMACtrl 11h Port DMA Size_H PortDMASize_H 12h Port DMA Size_M PortDMASize_M 13h Port DMA Size_L PortDMASize_L 14h Port Configuration_0 PortConfig_0 15h Port Configuration_1 PortConfig_1 16h Reserved 17h USB Ind...

Page 16: ... 2Ah SCSI Mode 1 SCSIMODE1 2Bh SCSI Control SCSICTL 2Ch SCSI Synchronous data transfer Mode SCSIDATA 2Dh SCSI DATA SYNCMODE 2Eh SCSI Own ID OWNID 2Fh SCSI Source Destination ID SDID 30h SCSI Selection Timeout Counter SELTIME 31h SCSI FIFO Control FIFOCTL 32h SCSI FIFO Data FIFODATA 33h SCSI Non DMA Transfer Size NDMASIZE 34h SCSI Command COMMAND 35h Reserved 36h Reserved 37h Reserved 38h Reserved ...

Page 17: ...PaIntStat Endpoint a status display clear 2h EPbIntStat Endpoint b status display clear 3h EPcIntStat Endpoint c status display clear Details appearing in IntEnbWindow_0 06h IntIndex 08h higher order 4 bits bit7 6 5 4 Function of IntEnbWindow_0 register Description on display 0h EP0IntEnb Endpoint 0 status interrupt enabled 1h EPaIntEnb Endpoint a status interrupt enabled 2h EPbIntEnb Endpoint b s...

Page 18: ...PrFIFOremain EP r r a b c FIFO counter USBWindow_6 1Eh EPrFIFOforCPU EP r r a b c FIFO for CPU access USBWindow_7 1Fh EPrFIFOCtrl EP r r a b c FIFO control 08h USBWindow_0 18h EP0_SETUP_0 EP0 SETUP stage receive data USBWindow_1 19h EP0_SETUP_1 EP0 SETUP stage receive data USBWindow_2 1Ah EP0_SETUP_2 EP0 SETUP stage receive data USBWindow_3 1Bh EP0_SETUP_3 EP0 SETUP stage receive data USBWindow_4 ...

Page 19: ...o Suspend Send Wakeup xINT mode1 xINT mode0 0Ah R W USBCommon xxh VBUS IgnrTgl Mis EnPull Up Active USB 0Bh R W 00h 0Ch R W 00h 0Dh R W Reset 00h PORT SCSI USB 0Eh R W 00h 0Fh R W 00h 10h R W PortDMACtrl 00h MODE1 MODE0 S_FIFO DTGO 11h R W PortDMASize_H 00h DBC23 DBC22 DBC21 DBC20 DBC19 DBC18 DBC17 DBC16 12h R W PortDMASize_M 00h DBC15 DBC14 DBC13 DBC12 DBC11 DBC10 DBC9 DBC8 13h R W PortDMASize_L ...

Page 20: ...R W SCSICTL 00h ACK ATN SEL BSY REQ MSG I O C D 2Ch R W SCSIDATA 00h DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 2Dh R W SYNCMODE 00h RATE3 RATE2 RATE1 RATE0 OFF3 OFF2 OFF1 OFF0 2Eh R W OWNID 00h OID2 OID1 OID0 2Fh R W SDID xxh SID2 SID1 SID0 DID2 DID1 DID0 30h R W SELTIME 00h ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 31h R W FIFOCTL 01h FCLR FULL EMPTY 32h R W FIFODATA xxh FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 33h R W NDMAS...

Page 21: ...r OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv 3h EPcIntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK INtolkenRcv OUTtolkenRcv Details appearing in IntEnbWindow_0 06h IntIndex 08h Higher order 4 bits bit7 6 5 4 IntStatWindow_0 Functions of register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0h EP0IntStat INtranACK OUTtranACK INtranErr OUTtranErr INtranNAK OUTtranNAK ...

Page 22: ..._1 19h EPrConfig_ OUTxIN MaxPacketSize 3 0 USBWindow_2 1Ah EPrControl INForce NAK InForce STALL InEnShort Pkt InToggle Stat InToggle Clr InToggle Set USBWindow_3 1Bh Reserved OutForce NAK OutForce STALL OutToggle Stat OutToggle Clr OutToggle Set USBWindow_4 1Ch Reserved USBWindow_5 1Dh EPrFIFOremain MSB EP0FIFOremainCounter 7 0 LSB USBWindow_6 1Eh EPrFIFOforCPU MSB EP0FIFOdata 7 0 LSB USBWindow_7 ...

Page 23: ...HIGH Clearing GoSuspend clears it BIT6 USB Reset At USB reset this bit becomes HIGH At the same time the USB address register shown in 7 5 2 1 USB Address USBAddress is cleared BIT5 USB Suspend At USB Suspend this bit becomes HIGH BIT4 Detect SOF Token When the SOF Token is detected this bit becomes HIGH BIT3 Port DMA Complete This bit becomes HIGH when a port DMA transfer activated by the PortDMA...

Page 24: ...atus BIT3 Endpoint c Interrupt Status This bit becomes HIGH when an interrupt factor related to the USB interface shown in the EPcIntStat register is present BIT2 Endpoint b Interrupt Status This bit becomes HIGH when an interrupt factor related to the USB interface shown in the EPbIntStat register is present BIT1 Endpoint a Interrupt Status This bit becomes HIGH when an interrupt factor related t...

Page 25: ...on to the CPU is enabled Address Register Name Bit Symbol Description 04h MainIntEnb 7 EnUSBresume Enable USB Resume 6 EnUSBreset Enable USB Reset 5 EnUSBsuspend Enable USB Suspend 4 EnDetectSOF Enable Detect SOF 3 EnPortDMACmp Enable Port DMA Complete 2 EnSCSI Enable SCSI Interrupt 1 EnRcvSETUP Enable Received SETUP 0 EnEPrIntStat Enable EPr Interrupt Status BIT2 Enable SCSI Interrupt When this b...

Page 26: ...Index_1 of the IntIndex register 08h For set value of the IntIndex register refer to section 7 4 Detailed Description of Set Values of IntIndex Register Address Register Name Bit Symbol Description 07h IntEnbWindow_1 7 IntEnbWindow_1 7 6 IntEnbWindow_1 6 5 IntEnbWindow_1 5 4 IntEnbWindow_1 4 3 IntEnbWindow_1 3 2 IntEnbWindow_1 2 1 IntEnbWindow_1 1 0 IntEnbWindow_1 0 Interrupt Enable Window 1 7 3 9...

Page 27: ... interrupt and becomes Hi Z condition when negating it 7 3 11 USB Common USBCommon R W Sets operation of the USB interface Address Register Name Bit Symbol Description 0Ah USBCommont 7 VBUS VBUS 6 0 Reserved 5 0 Reserved 4 0 Reserved 3 0 Reserved 2 IgnrTglMis Ignore Toggle Mismatch 1 EnPullUp Enable Pull Up 0 ActiveUSB Active USB Interface BIT7 VBUS Shows the state of the VBUS signal 0 Disconnecte...

Page 28: ... transfer between the port and USB 0 1 Performs DMA transfer between the port and SCSI 1 0 Performs DMA transfer between SCSI and USB 1 1 Reserve Setting disabled BIT1 SCSI FIFO Control Concurrent setting of this bit and DTGO to HIGH does not cause DMA transfer by hardware Instead the CPU transfers while monitoring the state of SCSI FIFO 31 32H The CPU must read or write data from or into SCSI FIF...

Page 29: ...M R W Sets the second byte of the byte length 3 bytes for port DMA transfer Address Register Name Bit Symbol Description 12h PortDMASize_M 7 PortDMASize 15 6 PortDMASize 14 5 PortDMASize 13 4 PortDMASize 12 3 PortDMASize 11 2 PortDMASize 10 1 PortDMASize 9 0 PortDMASize 8 Port DMA Size Middle 7 3 16 Port DMA Size Low PortDMASize_L R W Sets the least significant byte of the byte length 3 bytes for ...

Page 30: ...termines the operation mode of the port interface 0 Master mode PDREQ input XPDACK XPRD XPWR output 1 Slave mode PDREQ output XPDACK XPRD XPWR input BIT3 PDREQ level Determines the operation level of the PDREQ signal 0 Positive logic 1 Negative logic BIT2 Swap Port Interface Bus Swaps higher order 8 bits with the lower ones when the port interface with 16 bits wide is used 0 Higher order 1 byte da...

Page 31: ...to 8 is discarded when the first one word is transferred and only PD7 to 0 is transferred PD15 to 8 is used when the last data to be transferred is not a word but a byte BUS8 1 Only PD7 to 0 is used for transfer PD15 to 8 goes into Input mode connect to GND or HVDD 7 3 18 Port Config 1 PortConfig_1 R W Sets the operation mode of the port interface Address Register Name Bit Symbol Description 15h P...

Page 32: ...play by set values of the USBIndex register refer to section 7 5 Detailed Description of Set Values of USBIndex Register Address Register Name Bit Symbol Description 18h USBWindow_0 7 USBWindow_0 7 6 USBWindow_0 6 5 USBWindow_0 5 4 USBWindow_0 4 3 USBWindow_0 3 2 USBWindow_0 2 1 USBWindow_0 1 0 USBWindow_0 0 USB Window 0 7 3 21 USB Window 1 USBWindow_1 R W Displays the USB related register The reg...

Page 33: ...ue set at USBIndex register 17h For details of display by set values of the USBIndex register refer to section 7 5 Detailed Description of Set Values of USBIndex Register Address Register Name Bit Symbol Description 1Bh USBWindow_3 7 USBWindow_3 7 6 USBWindow_3 6 5 USBWindow_3 5 4 USBWindow_3 4 3 USBWindow_3 3 2 USBWindow_3 2 1 USBWindow_3 1 0 USBWindow_3 0 USB Window 3 7 3 24 USB Window 4 USBWind...

Page 34: ...ue set at USBIndex register 17h For details of display by set values of the USBIndex register refer to section 7 5 Detailed Description of Set Values of USBIndex Register Address Register Name Bit Symbol Description 1Eh USBWindow_6 7 USBWindow_6 7 6 USBWindow_6 6 5 USBWindow_6 5 4 USBWindow_6 4 3 USBWindow_6 3 2 USBWindow_6 2 1 USBWindow_6 1 0 USBWindow_6 0 USB Window 6 7 3 27 USB Window 7 USBWind...

Page 35: ...XECUTING SCSI COMMAND This bit is HIGH during execution of the SCSI control command This bit does not cause an interruption to the CPU Even when it becomes HIGH no interruption is output It is used to monitor the state of execution of the SCSI control command BIT4 SCSI INTERRUPT STATUS 1 This bit becomes HIGH when there is any factor responsible for an interruption related to the SCSI interface sh...

Page 36: ...w Only one ID bit is asserted or Three or more ID bits are asserted BIT5 SELECTION TIME OUT This bit becomes HIGH when time out is detected during the selection or reselection phase BIT4 SCSI ATN ASSERTION DETECTED This bit becomes HIGH when SCSI ATN is asserted It is not set however in the regular sequence of assertion of SCSI ATN In other words this bit is not set in the message out phase immedi...

Page 37: ...chronous transfer The offset error means that the offset counter is not reset to 0 when transfer ends or that the counter overflows underflows BIT4 UNDEFIND GROUP COMMAND This bit becomes HIGH when SCSI command other than group 0 1 2 or 5 is received BIT3 COMMAND ERROR This bit becomes HIGH when other control command is issued during execution of the command although an undefined SCSI control comm...

Page 38: ...errupt occurs The bit setting is also valid in FIFO DMA mode BIT2 AUTO2 status message stop Executes automatically STS_MSG after executing the DMA_DATA_IN OUT command At the end of execution ASCMP interrupt occurs The bit setting is also valid in FIFO DMA mode AUTO During execution of AUTO1 or 2 the AUTO bit of the SCSIMODE1 register is assumed to be 1 The EXEC bit also becomes 1 during execution ...

Page 39: ...et mode BIT4 AUTO SEND STATUS MESSAGE When this bit is HIGH it puts the SCSI control command Status_Message into Automatic Transmission mode In this mode the FLAG and LINK bits of the SCSI command block which have been received are checked When the LINK bit is LOW status 00h GOOD and message 00h COMMAND COMPLETE are automatically sent When the LINK bit is LOW status 10h INTERMEDIATE GOOD and messa...

Page 40: ... 4 BSY SCSI BSY 3 REQ SCSI REQ 2 MSG SCSI MSG 1 I O SCSI I O 0 C D SCSI C D 7 3 34 SCSI Data SCSIDATA R W This register is accessed when the CPU directly controls the SCSI data bus For such direct control DIRECT bit 1 must be set in the mode setting register 0Ah The status of each signal is stored as active high The DIRECT setting does not determine whether the parity bit is output or not It is ou...

Page 41: ...001 2T 1T 1T 2T 3T Note 2 0001 1 0010 2T 2T 4T 0010 2 0011 3T 2T 5T 0011 3 0100 3T 3T 6T 0100 4 0101 4T 3T 7T 0101 5 0110 4T 4T 8T 0110 6 0111 5T 4T 9T 0111 7 1000 5T 5T 10T 1000 8 1001 6T 5T 11T 1001 9 1010 6T 6T 12T 1010 10 1011 7T 6T 13T 1011 11 1100 7T 7T 14T 1100 12 1101 8T 7T 15T 1101 13 1110 8T 8T 16T 1110 14 1111 9T 8T 17T 1111 15 Note 1 T is a cycle double the internal clock 40MHz Note 2 ...

Page 42: ...the initiator SCSI ID to be re selected in DESTINATION ID When selection is received the initiator SCSI ID that makes a selection is set in SOURCE ID 7 3 38 Selection Timeout Counter SLTIME R W Sets time out delay for selection and re selection Address Register Name Bit Symbol Description 30h SLTIME 7 ST7 MSB 6 ST6 5 ST5 4 ST4 Selection Time out Counter 3 ST3 2 ST2 1 ST1 0 ST0 MSB The time out del...

Page 43: ...O is ignored BIT0 EMPTY When this bit is HIGH it means that SCSI FIFO is empty In this state any attempt to read data from SCSI FIFO results in invalid data read out 7 3 40 FIFO Data FIFODATA R W This register allows access to SCSI FIFO from the CPU Address Register Name Bit Symbol Description 32h FIFODATA 7 FD7 MSB 6 FD6 5 FD5 4 FD4 SCSI_FIFO data 3 FD3 2 FD2 1 FD1 0 FD0 LSB 7 3 41 Non DMA Transf...

Page 44: ...sting an LSI Basically writing into this register is inhibited Address Register Name Bit Symbol Description 3Eh TEST 7 TM2 6 TM1 5 TM0 4 USEL1 3 USEL0 2 OFST 1 SCBC 0 DMBC 7 3 44 Revision Reg REVISION R Shows the revision No of the IC Address Register Name Bit Symbol Description 3Fh REVISION 7 REV7 MSB 6 REV6 5 REV5 4 REV4 REVISION 3 REV3 2 REV2 1 REV1 0 REV0 LSB In normal Read mode the register a...

Page 45: ...IntStat 7 INtranACK IN Transaction ACK EPbIntStat EPcIntStat 6 OUTtranACK OUT Transaction ACK 5 INtranErr IN Transaction Error 4 OUTtranErr OUT Transaction Error 3 INtranNAK IN Transaction NAK 2 OUTtranNAK OUT Transaction NAK 1 INtokenRcv IN Token Received 0 OUTtokenRcv OUT Token Received BIT7 IN Transaction ACK This bit becomes HIGH when ACK is received during IN Transaction BIT6 OUT Transaction ...

Page 46: ...e CPU is enabled IntIndex_n 0h to 3h Address Register Name Bit Symbol Description 07h 08h EP0IntStat EPaIntStat 7 EnINtranACK Enable IN Transaction ACK EPbIntStat EPcIntStat 6 EnOUTtranCmp Enable OUT Transaction Complete 5 EnINtranErr Enable IN Transaction Error 4 EnOUTtranErr Enable OUT Transaction Error 3 EnINtranNAK Enable IN Transaction NAK 2 EnOUTtranNAK Enable OUT Transaction NAK 1 EnINtoken...

Page 47: ...nControl 1Bh EP0OutControl 1Ch Reserved 1Dh EP0FIFOremain 1Eh EP0FIFOforCPU 1Fh EP0FIFOCtrl 01h to 07h 18h EPrConfig_0 19h EPrConfig_1 1Ah EPrControl 1Bh Reserved 1Ch Reserved 1Dh EP r FIFOremain 1Eh EP r FIFOforCPU 1Fh EP r FIFOCtrl 08h 18h EP0_SETUP 0 19h EP0_SETUP 1 1Ah EP0_SETUP 2 1Bh EP0_SETUP 3 1Ch EP0_SETUP 4 1Dh EP0_SETUP 5 1Eh EP0_SETUP 6 1Fh EP0_SETUP 7 09h 18h FrameNumber_H 19h FrameNum...

Page 48: ...dex 00h Address Register Name Bit Symbol Description 19h EP0Config_1 7 OUT IN OUT IN 6 0 Reserved 5 0 Reserved 4 0 Reserved 3 MaxPacketSize 3 2 MaxPacketSize 2 Max Packet Size 1 MaxPacketSize 1 0 MaxPacketSize 0 BIT7 OUT IN Sets the direction of transfer of Endpoint 0 Set the direction of transfer in data stage by interpreting the request in SETUP stage After completion of setting of the direction...

Page 49: ...us stage is ready When there is a transaction that is being executed setting of this bit a fixed period of time after starting transaction becomes valid from the next transaction BIT6 IN Transaction Force STALL When this bit is set to HIGH it becomes valid taking precedence over the setting of the INForceNAK bit Setting this bit to HIGH returns STALL to IN Transaction When the RcvEP0SETUP bit of t...

Page 50: ...sfer of data stage is OUT the data stage can be executed by clearing this bit to LOW after the status stage is ready When there is a transaction that is being executed setting of this bit a fixed period of time after starting transaction becomes valid from the next transaction BIT6 OUT Transaction Force STALL When this bit is set to HIGH it becomes valid taking precedence over the setting of the I...

Page 51: ...inCount 2 1 EP0FIFOremainCount 1 0 EP0FIFOremainCount 0 7 5 2 6 EP0 FIFO for CPU EP0FIFOforCPU R W This register allows access to FIFO of Endpoint 0 from the CPU When the EnFiFOwr bit of the EP0FIFOCtrl register is set writing is enabled when the EnFIFOrd bit is set reading is enabled It should be noted that reading or writing decreases the number of data in FIFO USBIndex 00h Address Register Name...

Page 52: ... a writing operation into FIFO is carried out in this state the data is ignored BIT5 FIFO Clear Setting this bit to HIGH clears data stored in FIFO The bit returns to LOW automatically after clearing BIT4 ALL FIFO Clear Setting this bit to HIGH clears FIFO of all Endpoints When the MaxPacketSize filed or DoubleBuf bit of each Endpoint is set be sure to set this bit to HIGH once after completion of...

Page 53: ... bit becomes LOW at all endpoints BIT0 Really Used Setting this bit to HIGH allows to use the endpoints When this bit is LOW it ignores access to the endpoint Set in accordance with the SetConfiguration request from the host 7 5 2 9 EP r r a b c Config 1 EPrConfig_1 R W Sets operation of Endpoints a b and c USBIndex 01h to 03h Address Register Name Bit Symbol Description 19h EPrConfig_1 7 DoubleBu...

Page 54: ...LL Setting this bit to HIGH returns STALL to transaction Setting this bit to HIGH gives a STALL response to transaction When there is a transaction that is being executed setting of this bit a fixed period of time after starting transaction becomes valid from the next transaction BIT5 Short Packet IN Transaction Only Setting this bit to HIGH returns packet to IN Transaction independent of amount o...

Page 55: ...remainCount 1 0 EPrFIFOremainCount 0 7 5 2 12 EPr FIFO for CPU EPrFIFOforCPU R W This register allows access to FIFO of the endpoint from the CPU When the EnFiFOwr bit of the EP0FIFOCtrl register is set writing is enabled when the EnFIFOrd bit is set reading is enabled It should be noted that reading or writing causes changes in the number of data in FIFO as it is similar to access from the USB US...

Page 56: ...tate the data is ignored BIT5 FIFO Clear Setting this bit to HIGH clears data stored in FIFO The bit returns to LOW automatically after clearing BIT2 AutoForceNAK Setting this bit to HIGH sets the InForceNAK bit of the EP0InControl register and the OutForceNAK bit of the EP0OutControl register when transaction is completed normally BIT1 Enable FIFO Write Setting this bit to HIGH enables writing da...

Page 57: ...rved 5 0 Reserved 4 0 Reserved 3 0 Reserved 2 FrameNumber_ 10 1 FrameNumber_ 9 Frame Number High 0 FrameNumber_ 8 7 5 2 16 Frame Number L FrameNumber_L R Displays lower order 8 bits in the FrameNumber field of the SOF Packet received USBIndex 09h Address Register Name Bit Symbol Description 19h FrameNumber_L 7 FrameNumber_ 7 6 FrameNumber_ 6 5 FrameNumber_ 5 4 FrameNumber_ 4 Frame Number Low 3 Fra...

Page 58: ...er aborting the process The SABT bit of the MAININT register is set The status block is set It causes an interruption If this command is issued in the state of not operating it is ignored Assert_RST 04H Asserts the SCSI RST signal XSRST for 768 T 2 about 46µs and then negates it This command releases all the signals it asserts causing the busfree condition The inside of the IC is not initialized I...

Page 59: ...ing into the selection phase It terminates selection and operation when its counterpart asserts XSBSY After completion it sets the GOOD bit of the MAININT register It causes an interruption After that the IC goes into Initiator mode Select_WithATN_Command 0AH Asserts SCSI ATN signal executes selection and then executes the message out command phase This command is valid in both disconnected and co...

Page 60: ...egister and clear it when the command is terminated After issuing the command the IC operates as follows 1 Waits for the selection phase 2 When selected checks XSATN If it is not asserted the IC operates as mentioned in 5 If it is asserted the IC sets the message out phase and receives a message 3 If the message received is other than Identify the IC operates as mentioned in 6 The CPU checks the m...

Page 61: ...s or longer and after that it operates as in the case of Wait_Select_Command 0Ch After that the IC goes into Target mode Negate_ACK 11H Clears ACK left asserted by the last message transfer in Initiator mode when the LSI stops operation Command_Out 12H Executes the SCSI command phase Valid only in the connected condition It can be issued in either Target or Initiator mode Issuing this command in t...

Page 62: ... is found when the data out phase is checked ILPHS of SCSIINT1 is set and an interruption is caused Non DMA_Data_Out 14H Valid only when the command is connected which executes the data out phase between SCSI and CPU interface It can be issued in either Target or Initiator mode Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an interruption In Target ...

Page 63: ...e It can be issued in either Target or Initiator mode Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an interruption In Target mode Sets the number of transfer in the NON DMA data size register and issues this command The CPU writes data into FIFO by check the status of FIFO The IC operates as follows Outputs data equivalent to the number of bytes se...

Page 64: ...In Initiator mode The CPU sets the number of bytes of the message to be received in the NON DMA data size register before issuing this command The IC operates as follows At the start of execution negates XSACK if it is asserted Enters the message equivalent to the number of bytes into FIFO after checking the message in phase at the timing when REQ is asserted When FIFO is full the REQ ACK handshak...

Page 65: ...tiator mode Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an interruption In Target mode Writes the status and message to be sent into FIFO and issues this command The status and message may be written after issuing the command The IC operates as follows Sets the status phase fetches 1 byte status byte from FIFO and transfers it Sets the message in ...

Page 66: ...ition where no SCSI control command is being executed If they are issued while SCSI control command is in execution a command error occurs 7 7 Others and Cautions in Operation Operation responding to the selection without the SCSI 1 arbitration phase The IC operates as mentioned below in response to the selection of only target ID of SCSI 1 Note that there occurs no automatic transition to the mes...

Page 67: ...and subsequent command stop causes negation of PDREQ being output to the port interface at the internal timing of the IC Accordingly use such setting after checking that it causes no problem in handshake on the LSI side connected to the IC In such a case no problem occurs in the internal sequence of the IC if XPDACK or XPRD XPWR may come from the port side Though data transfer to and from FIFO may...

Page 68: ... voltage HVDD 4 50 5 00 5 50 V LVDD 3 00 3 30 3 60 Input voltage HVIN VSS HVDD V LVIN VSS LVDD V Operating temperature Topr 0 25 70 C Input signal rise time Normal input tri 50 ns Input signal fall time Normal input tfi 50 ns Input signal rise time Schmitt input tri 5 ms Input signal fall time Schmitt input tfi 5 ms 8 3 DC Characteristics 1 I O characteristics in the DC condition Ta 0 to 70 C VSS ...

Page 69: ...vered XRESET XSREQ XSACK XSDB0 to 7 XSDBP XCS XRD XWR XPRD XPWR XPDACK PDREQ Item Symbol Conditions Min Typ Max Unit HIGH level trigger Input voltage VT2 HVDD 5 5V LVDD 3 6V 1 2 2 4 V LOW level trigger Input voltage VT2 HVDD 4 5V LVDD 3 0V 0 6 1 8 V Hysteresis voltage VH HVDD 5 0V LVDD 3 3V 0 1 V 5 TTL Schmitt input characteristics USB Ta 0 to 70 C VSS 0V Names of signals covered DP DM Item Symbol...

Page 70: ...in Typ Max Unit HIGH level Output voltage VOH HVDD 5 0V IOH 1 5mA HVDD 0 4 V LOW level Output voltage VOL HVDD 4 5V IOL 3mA 0 4 V 10 Output characteristics Ta 0 to 70 C VSS 0V IOL 6mA Names of signals covered XINTU XINTS PDREQ Item Symbol Conditions Min Typ Max Unit HIGH level Output voltage VOH HVDD 5 0V IOH 3mA HVDD 0 4 µA LOW level Output voltage VOL HVDD 4 5V IOL 6mA 0 4 V 11 Output characteri...

Page 71: ...SI 3 Fast20 14 Output characteristics Ta 0 to 70 C VSS 0V Names of signals covered DP DM Item Symbol Conditions Min Typ Max Unit HIGH level Output voltage VOH LVDD Min IOH 0 5mA 2 8 V LOW level Output voltage VOL LVDD Min IOL 3 0mA 0 3 V 8 4 AC Characteristics Measurement conditions of AC characteristics Ta 0 to 70 C HVDD 5V 10 LVDD 3 3V 0 3V VSS 0V DC level to determine input 0 8V to 2 4V Operati...

Page 72: ...4 0 Invalid XRD rise XCS rise 0 ns T103 XRD LOW level pulse width 65 ns T104 XRD HIGH level pulse width 45 ns Normal Registers other than those below 65 T105 XRD fall DB 7 0 output FIFO area for USB 1 2 120 ns T106 XRD rise DB 7 0 hold 2 15 ns 1 The FIFO area for USB indicates acess to USBWindow_6 1Eh in case of USBIndex 17h 00h to 03h T101 T105 T103 T104 T106 T102 XCS AD 4 0 DB 7 0 XRD ...

Page 73: ... Normal Registers other than those below FIFO area_A for USB 1 FIFO area_B for USB 2 45 80 120 ns T115 DB 7 0 valid XWR rise 10 ns T116 XWR rise DB 7 0 hold 0 ns 1 When written into FIFO area for USB see the previous page and the next access also writes into FIFO area for USB 2 When written into FIFO area for USB see the previous page and the next access reads FIFO area for USB or reads the FIFO f...

Page 74: ...ecification Min Typ Max Unit T201 XSBSY IN XSBSY OUT OWNID valid 1600 ns T202 XSBSY OUT XSSEL 3000 ns T203 XSSEL SELID valid 1500 ns T204 SELID valid XSBSY OUT 150 ns T205 XSBSY OUT XSBSY IN 500 ns T206 XSBSY IN XSSEL 250 ns XSBSY IN XSSEL XSBSY OUT XSDB0 7 P XSATN XSIO T201 T202 T203 T204 T206 T205 ...

Page 75: ...t T207 XSBSY IN XSBSY OUT OWNID valid 1600 ns T208 XSBSY OUT XSSEL 3000 ns T209 XSSEL SELID valid XSIO 1500 ns T210 SELID valid XSBSY OUT 150 ns T211 XSBSY OUT XSBSY IN 500 ns T212 XSBSY IN XSBSY OUT 100 ns T213 XSBSY OUT XSSEL 150 ns XSBSY IN XSSEL XSDB0 7 P XSIO T207 T208 T209 T210 T211 T212 T213 XSBSY OUT ...

Page 76: ... 70 EPSON Rev 1 0 8 4 2 3 Timing of Being Selected Symbol Specification Min Typ Max Unit T214 SELID valid XSBSY IN 0 ns T215 XSBSY IN XSBSY OUT 800 ns T216 XSBSY OUT XSSEL 0 ns XSBSY IN XSBSY OUT XSSEL XSDB0 7 P T215 T216 T214 ...

Page 77: ... 4 2 4 Timing of Being Selected Symbol Specification Min Typ Max Unit T217 SELID valid XSBSY IN 0 ns T218 XSBSY IN XSBSY OUT 800 ns T219 XSBSY OUT XSSEL 0 ns T220 XSSEL XSBSY OUT 200 ns XSBSY IN XSSEL XSBSY OUT XSDB0 7 P XSIO T218 T219 T220 T217 ...

Page 78: ...echnical Manual 72 EPSON Rev 1 0 8 4 2 5 XSATN Output Timing Symbol Specification Min Typ Max Unit T221 XSREQ XSATN 25 ns T222 XSATN XSACK 150 ns XSATN XSREQ XSACK XSDB0 7 P XSMSG XSIO XSCD LAST MESSAGE T221 T222 ...

Page 79: ... 4 2 6 Initiator Asynchronous Data out Timing Data output Symbol Specification Min Typ Max Unit T223 XSREQ XSACK 25 ns T224 XSDB valid XSACK 100 ns T225 XSREQ XSACK 25 90 ns T226 XSACK XSDB invalid 50 ns XSDB0 7 P XSREQ XSACK T224 T226 T223 T225 ...

Page 80: ... 8 4 2 7 Initiator Asynchronous Data in Timing Data input Symbol Specification Min Typ Max Unit T227 XSDB valid XSREQ 30 ns T228 XSREQ XSACK 25 ns T229 XSACK XSDB invalid 0 ns T230 XSREQ XSACK 25 90 ns XSDB0 7 P XSREQ XSACK T227 T229 T228 T230 ...

Page 81: ...r Synchronous Data out Timing Data output Symbol Specification Min Typ Max Unit T231 XSDB valid XSACK 25 ns T232 XSACK XSDB invalid 25 ns T233 XSACK XSACK 25 ns T234 XSACK NEXT XSACK 25 ns Note Value when RATE3 to 0bit is 0000 The timing of switching data is the same as in the case of XSREQ rise ...

Page 82: ... 8 4 2 9 Initiator Synchronous Data in Timing Data input Symbol Specification Min Typ Max Unit T235 XSDB0 7 P valid XSREQ 6 5 ns T236 XSREQ XSDB0 7 P invalid 5 ns T237 XSREQ XSREQ 11 ns T238 XSREQ XSREQ 11 ns XSDB0 7 P XSREQ T235 T236 T237 T238 ...

Page 83: ...ynchronous Data in Timing Data output Symbol Specification Min Typ Max Unit T239 XSDB valid XSREQ 100 ns T240 XSACK XSREQ 25 90 ns T241 XSREQ XSDB invalid 50 ns T242a XSACK NEXT XSREQ 25 ns T242b XSREQ XSREQ 150 ns XSDB0 7 P XSREQ XSACK T239 T241 T240 T242a T242b ...

Page 84: ... Asynchronous Data out Timing Data input Symbol Specification Min Typ Max Unit T243 XSDB valid XSACK 30 ns T244 XSACK XSREQ 25 90 ns T245 XSREQ XSDB invalid 0 ns T246a XSACK XSREQ 25 ns T246b XSREQ XSREQ 150 ns XSDB0 7 P XSREQ XSACK T243 T245 T244 T246a T246b ...

Page 85: ...output Symbol Specification Min Typ Max Unit T247 XSDB valid XSREQ 25 ns T248 XSREQ XSDB invalid 25 ns T249 XSREQ XSREQ 25 ns T250 XSREQ XSREQ 25 ns Note Value when RATE3 to 0bit is 0000 The timing of switching data is the same as in the case of XSREQ rise XSDB0 7 P XSREQ T247 T248 T249 T250 ...

Page 86: ...v 1 0 8 4 2 13 Target Synchronous Data out Timing Data input Symbol Specification Min Typ Max Unit T251 XSDB valid XSACK 6 5 ns T252 XSACK XSDB invalid 5 ns T253 XSACK XSACK 11 ns T254 XSACK XSACK 11 ns XSACK XSDB0 7 P T251 T252 T253 T254 ...

Page 87: ...time 0 ns T305 XPRD XPRD XPRD assert pulse width 30 ns T306 XPRD XPRD XPRD negate pulse width 30 ns T307 XPRD XPDACK XPRD hold time 0 ns T308 XPRD PD Data output delay time Note 1 0 25 ns T309 XPRD PD Hi Z Data bus negate time Note 1 6 40 ns Note 1 Data is output to PD only while both XPDACK and XPRD are asserted PD is always in Input mode except such time PDREQ 0 PRQLV 1 XPDACK I XPRD I PD15 0 0 ...

Page 88: ...te PDREQ negate delay time 10 37 ns T314 XPDACK XPWR XPWR setup time 0 ns T315 XPWR XPWR XPWR assert pulse width 30 ns T316 XPWR XPWR XPWR negate pulse width 30 ns T317 XPWR XPDACK XPWR hold time 0 ns T318 PD XPWR Data input delay time 10 ns T319 XPWR PD Data hold time 0 ns T313 T314 T315 T316 T317 T318 T311 T319 T312 PDREQ 0 PRQLV 1 XPDACK I XPWR I PD15 0 I XPRD I Direction of data transfer Prose...

Page 89: ... XPWR XPWR negate pulse width NP 2 25 ns T337 XPWR XPDACK XPWR hold time 0 5 ns T338 XPWR PD Data output delay time Note 1 0 25 ns T339 XPWR PD Hi Z Data bus negate time Note 1 5 40 ns T33A PDREQ negate XPDACK XPDACK setup time 5 ns Note 1 Data is output to PD only while both XPDACK and XPWR are asserted PD is always in Input mode except such time PDREQ I XPDACK 0 XPWR 0 PD15 0 0 T334 T335 T336 T3...

Page 90: ...up time 0 5 ns T345 XPRD XPRD XPRD assert pulse width AP 2 25 ns T346 XPRD XPRD XPRD negate pulse width NP 2 25 ns T347 XPRD XPDACK XPRD hold time 0 5 ns T348 PD XPRD Data input delay time 10 ns T349 XPRD PD Data hold time 0 ns T34A PDREQ negate XPDACK XPDACK setup time 5 ns PDREQ I XPDACK 0 XPRD 0 PD15 0 I T343 T34A T344 T345 T346 T347 T348 T349 Direction of data transfer Prosessor S1R72105 HOST ...

Page 91: ...ol Specification Min Typ Max Unit T400 CLK cycle 1 0 25 1 f ns T401 CLK HIGH width 1 10 1 f 0 4 15 1 f 0 6 ns T402 CLK LOW width 1 10 1 f 0 4 15 1 f 0 6 ns T403 CLK rise time 5 ns T404 CLK fall time 5 ns 1 T401 402 T400 1 Specified in the same rate also in any cases other than CLK input 20MHz T403 T404 T402 T400 T401 0 9V 1 9V ...

Page 92: ... 48MHz Note Maximum input voltage LVDD Symbol Specification Min Typ Max Unit T410 CLK cycle 1 20 83 ns T411 CLK HIGH width 1 8 33 12 5 ns T412 CLK LOW width 1 8 33 12 5 ns T413 CLK rise time 5 ns T414 CLK fall time 5 ns 1 T411 412 T410 0 9V 1 9V T410 T413 T414 T412 T411 ...

Page 93: ...XRESET Input Pulse Width Symbol Specification Min Typ Max Unit T420 XRESET LOW width 150 ns 8 4 4 4 USB Interface Access Timing Conformity to the USB 1 1 Specification For the USB1 1 Specification visit http www usb org developers docs html XRESET T420 ...

Page 94: ... 0 PDREQ PDREQ XPDACK XPDACK XPWR XPWR XPRD XPRD PORT Interface 5V type EXCLK CLKSEL 3 3V VC 100pF OSCIN 5pF OSCOUT 5pF TESTMON open 4 7kΩ 1MΩ 20 0MHz SCSI Interface active terminater DB 7 0 XSDB 7 0 DBP XSDBP ATN XSATN BSY XSBSY ACK XSACK RST XSRST MSG XSMSG SEL XSSEL C D XSCD REQ XSREQ I O XSIO XRESET XRESET HVDD 5V LVDD 3 3V VSS GND TESTEN GND GND GND 3pF GND GND USB Interface Use figure 2 VBUS...

Page 95: ...operation after checking that VBUS is HIGH 5V 3 How to handle DP and DM pins Add Zener diode for electrostatic protection onto the connector side Add 24 Ω resistor for adjusting impedance Add 22pF condensor for adjusting edge rate Add a diode onto the pin side to protect from a short in the wiring of the USB cable S1R72105 VBUS VBUS D D GND USB Connector Series B Receptacle 100kΩ GND GND 0 1µF 330...

Page 96: ...S1R72105 Technical Manual 90 EPSON Rev 1 0 10 EXTERNAL DIMENSIONS DRAWING Plastic QFP15 100 pin 14 0 1 16 0 4 51 75 26 50 INDEX Unit mm 0 18 25 1 100 76 1 0 5 0 2 0 10 0 125 0 5 0 1 0 05 0 05 0 025 ...

Page 97: ... 544 2490 FAX 34 93 544 2491 Scotland Design Center Integration House The Alba Campus Livingston West Lothian EH54 7EG SCOTLAND Phone 44 1506 605040 FAX 44 1506 605041 ASIA EPSON CHINA CO LTD 23F Beijing Silver Tower 2 North RD DongSanHuan ChaoYang District Beijing CHINA Phone 64106655 FAX 64107319 SHANGHAI BRANCH 7F High Tech Bldg 900 Yishan Road Shanghai 200233 CHINA Phone 86 21 5423 5577 FAX 86...

Page 98: ...In pursuit of Saving Technology Epson electronic devices Our lineup of semiconductors displays and quartz devices assists in creating the products of our customers dreams Epson IS energy savings ...

Page 99: ...First issue October 2002 Printed in Japan H A EPSON Electronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION SEIKO EPSON CORPORATION http www epsondevice com S1R72105 Technical Manual ...

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