S1R72105 Technical Manual
24
EPSON
Rev.1.0
7.3.17 Port Config 0 (PortConfig_0) R/W
Sets the operation mode of the IC.
Address
Register Name
Bit Symbol
Description
14h
PortConfig_0
7:ActivePort
Active Port
6: BUSC
Bus Configuration
5:PortSlave Port
Slave
4:0
Reserved
3:PDREQlevel PDREQ
level
2:Swap
Swap Port Interface Bus
1:OddStart
Odd Byte Start
0:Bus8
Port Interface 8 bit Bus
BIT7 Active Port
After reset, the port interface is in All Pins Input mode. Setting this bit to HIGH activates the port.
BIT6 Bus Configuration
Setting this bit to HIGH causes the listing order of DATA BUS of PORT interface in ascending order.
PIN No.
Bus Configuration
39 40 41 42 43 45 46 47 48 49 52 53 54 55 56 57
LOW
PD15 PD0 PD14 PD1 PD13 PD2 PD12 PD3 PD11 PD4 PD10 PD5 PD9 PD6 PD8 PD7
HIGH
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9
PD11 PD12 PD13 PD14 PD15
BIT5 Port Slave
Determines the operation mode of the port interface.
0: Master mode (PDREQ = input, XPDACK/XPRD/XPWR = output)
1: Slave mode (PDREQ = output, XPDACK/XPRD/XPWR = input)
BIT3 PDREQ level
Determines the operation level of the PDREQ signal.
0: Positive logic
1: Negative logic
BIT2 Swap Port Interface Bus
Swaps higher order 8 bits with the lower ones when the port interface with 16 bits wide is used.
0: Higher order 1 byte data appears in PD[7:0], lower order 1 byte data in PD[15:8].
Lower order 1 byte data is transferred first.
1: Higher order 1 byte data appears in PD[15:8], lower order 1 byte data in PD[7:0].
Higher-order 1 byte data is transferred first.
BIT1 Odd Byte Start
Setting this bit to HIGH causes the 8 bit-data to be transferred first, which is due to be sent later, because of the SWAP
setting when the port interface is used with 16 bits wide.
It is effective only for the first one byte only.
BIT0 Port Interface 8 bit Bus
Sets this bit to HIGH to use the port interface with 8 bits wide.
Only the lower 8 bits are valid. Connect the higher 8 bits to GND or HV
DD
externally.
