S1R72105 Technical Manual
Rev.1.0
EPSON
19
7.3.4 Interrupt Status Window 1(IntStatWindow_1) R/W
The endpoint interrupt status register appears.
The interrupt status to be displayed changes according to the value set at IntIndex_1 of the IntIndex register
(08h).
For set value of the IntIndex register, refer to section “7.4 Detailed Description of Set Values of IntIndex
Register.”
Address
Register Name
Bit Symbol
Description
03h IntStatWindow_1 7:
IntStatWindow_1[7]
6:
IntStatWindow_1[6]
5:
IntStatWindow_1[5]
4:
IntStatWindow_1[4]
3:
IntStatWindow_1[3]
2:
IntStatWindow_1[2]
1:
IntStatWindow_1[1]
0:
IntStatWindow_1[0]
Interrupt Status Window 1
7.3.5 Main Interrupt Enable (MainIntEnb) R/W
This register enables/disables interrupt factors of the MinInstStat register.
When the corresponding bit is set to HIGH an interruption to the CPU is enabled.
Address
Register Name
Bit Symbol
Description
04h
MainIntEnb
7: EnUSBresume
Enable USB Resume
6: EnUSBreset
Enable USB Reset
5: EnUSBsuspend
Enable USB Suspend
4: EnDetectSOF
Enable Detect SOF
3: EnPortDMACmp
Enable Port DMA Complete
2: EnSCSI
Enable SCSI Interrupt
1: EnRcvSETUP
Enable Received SETUP
0: EnEPrIntStat
Enable EPr Interrupt Status
BIT2 Enable SCSI Interrupt
When this bit is set to HIGH all SCSI interruptions including ASCMP are enabled. For DTCMP interruption by
SCSI, the BIT3 setting is valid instead of this bit.
7.3.6 EPr Interrupt Enable (EPrIntEnb) R/W
This register enables/disables interrupt factors of the EprIntStat register.
When the corresponding bit is set to HIGH an interruption to the CPU is enabled.
Address
Register Name
Bit Symbol
Description
05h
EPrIntEnb
7:
Reserved
6:
Reserved
5:
Reserved
4:
Reserved
3: EnEPcInt
Enable Endpoint c Interrupt
2: EnEPbInt
Enable Endpoint b Interrupt
1: EnEPaInt
Enable Endpoint a Interrupt
0: EnEP0Int
Enable Endpoint 0 Interrupt
