S1R72105 Technical Manual
Rev.1.0
EPSON
5
Pin No.
Symbol
I/O
Functional description
Remarks
CPU interface-related matters (19)
19
AD0
I
Address input pin (AD0 to AD5)
20 AD1
21 AD2
22 AD3
23 AD4
24 AD5
10
DB0
I/O
Data pin (DB0 to DB7)
11 DB1
12 DB2
13 DB3
15 DB4
16 DB5
17 DB6
18 DB7
Drive capability 3mA
31
XCS
Is
Chip select signal for accessing internal register
30
XINTU
O
USB interrupt request output signal
Drive capability 6mA
29
XINTS
O
SCSI interrupt request output signal
Drive capability 6mA
28
XRD
Is
Data read signal
27
XWR
Is
Data write signal
Others (17)
59
OSCIN
I
Input to built-in oscillation circuit (40MHz or 20MHz)
60
OSCOUT
O
Output from built-in oscillation circuit
8
TESTMON
O
Monitor output for testing (open LOW output usually)
Drive capability 2mA
32
XRESET
Ispu System reset input signal
9
TESTEN
Ipd
Pin for testing (connected to LOW (GND) usually)
63
CLKSEL
I
Input clock and PLL operation selection
HIGH (LV
DD
): Generates clock (SCSI_40MHz,USB_48MHz)
in internal PLL.
20MHz oscillation in OSCIN/OUT or input
20MHz(3.3V) to OSCIN
EXCLK is connected to LOW (GND) or HIGH
(LV
DD
).
LOW (GND): PLL stop (power-down) , external clock in
operation
40MHz oscillation in OSCIN/OUT or input
40MHz(3.3V) to OSCIN
Input 48MHz(3.3V) to EXCLK
62
EXCLK
I
External clock input pin for 3.3V level USB
(Connected to LOW (GND) or HIGH (LV
DD
) while it is not
used).
64 V
C
O
For instructions as to how to connect internal VCO control
pins, refer to the description of PLL circuit.
HV
DD
:5V (5)
14,33,44,51,
67,77,82,86,
90,94,98
HV
DD
P
Power supply for 5V interface
LV
DD
:3.3V (6)
1,26,61,76
LV
DD
P
Power supply for internal operation
V
SS
:0V (17)
4,25,38,50,
58,65,69,72,
75,79,84,88,
92,96,100
V
SS
P
GND
(Note)
I
: Input
O
: Output
Is
: Schmitt input
Ood
: Open-drain output
Ipu
: Pull-up input
Otr
: Try state output
Ispu
: Pull-up Schmitt input
Ipd
: Pull-down input
