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Epson Research and Development

Page 23

Vancouver Design Center

Hardware Functional Specification

S1D13503

Issue Date: 01/01/29

X18A-A-001-08

IOW#

I

85

82

104

TTLS

In MC68000 MPU interface, this pin is connected to the R/W#
pin of MC68000. This input pin defines whether the data
transfer is a read (active high) or write (active low) cycle. In
other MPU/Bus interfaces, this is the active low input to write
data into an internal register.

IOR#

I

86

83

106

TTLS

In MC68000 MPU interface, this pin is connected to the AS#
pin of MC68000. This input pin indicates a valid address is
available on the address bus. In other MPU/Bus interfaces, this
is the active low input to read data from an internal register.

MEMCS#

I

87

84

107

TTLS

Active low input to indicate a memory cycle.

MEMW#

I

88

85

109

TTLS

Active low input to indicate a memory write cycle. This pin
should be tied to V

DD

in an MC68000 MPU interface.

MEMR#

I

89

86

110

TTLS

Active low input to indicate a memory read cycle. This pin
should be tied to V

DD

in an MC68000 MPU interface.

READY

O

90

87

112

TS3

For MC68000 MPU interface, this pin is connected to the
DTACK# pin of MC68000 and is driven low when the data
transfer is complete. In other MPU/Bus interfaces, this output
is driven low to force the system to insert wait states when
needed.

READY is placed in a high impedance (Hi-Z) state after the
transfer is completed.

RESET

I

32

29

37

TTLS

Active high input to force all signals to their inactive states.

Table 5-1: Bus Interface

Pin Name

Type

F00A
Pin #

F01A
Pin #

D00A
Pad #

Driver

Description

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Summary of Contents for S1D13503 Series

Page 1: ...use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trad...

Page 2: ...Page ii Epson Research and Development Vancouver Design Center S1D13503 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 3: ... Engineering Support Application Engineering Support Engineering and Sales Support is provided by Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Taiwan R O C Epson Taiwan ...

Page 4: ...Page iv Epson Research and Development Vancouver Design Center S1D13503 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 5: ...ILITIES 13503SHOW EXE Display Utility 13503VIRT EXE Display Utility 13503BIOS COM Display Utility 13503MODE EXE Display Utility 13503PD EXE Power Down Utility 13503READ EXE Diagnostic Utility EVALUATION S5U13503B00C Rev 1 Evaluation Board User Manual APPLICATION NOTES Power Consumption ISA Bus Interface Considerations MC68340 Interface Considerations LCD Panel Options Memory Requirements S1D13503 ...

Page 6: ...Page vi Epson Research and Development Vancouver Design Center S1D13503 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 7: ... map ping to access one of sixteen internal registers Memory Interface 8 16 bit SRAM interface configurations 128K bytes using one 64Kx16 SRAMs 128K bytes using two 64Kx8 SRAMs 64K bytes using two 32Kx8 SRAMs 40K bytes using one 8Kx8 and one 32Kx8 SRAM 32K bytes using one 32Kx8 SRAM 16K bytes using two 8Kx8 SRAMs 8K bytes using one 8Kx8 SRAM Display Modes Black and white display 2 4 bits per pixel...

Page 8: ...e 039192 Tel 337 7911 Fax 334 2716 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Copyright 1997 2001 Epson Research and Development Inc All rights reserved VDC Information in this document is s...

Page 9: ...n use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other tr...

Page 10: ...on Research and Development Vancouver Design Center S1D13503 Hardware Functional Specification X18A A 001 08 Issue Date 01 01 29 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 11: ...slation 15 3 5 2 Control Registers 15 3 5 3 Sequence Controller 15 3 5 4 LCD Panel Interface 15 3 5 5 Look Up Table 16 3 5 6 Port Decoder 16 3 5 7 Memory Decoder 16 3 5 8 Data Bus Conversion 16 3 5 9 Address Generator 16 3 5 10 MPU CRT Selector 16 3 5 11 Display Data Formatter 16 3 5 12 Clock Inputs Timing 16 3 5 13 SRAM Interface 16 4 PINOUT DIAGRAM 17 5 PIN DESCRIPTION 22 5 1 Description 22 5 2 ...

Page 12: ... Panels Format 1 50 7 4 6 LCD Interface Options 52 8 HARDWARE REGISTER INTERFACE 61 8 1 Register Descriptions 61 8 2 Look Up Table Architecture 72 8 2 1 Gray Shade Display Modes 72 8 2 2 Color Display Modes 74 8 3 Power Save Modes 77 8 3 1 Power Save Mode 1 77 8 3 2 Power Save Mode 2 77 8 3 3 Power Save Mode Function Summary 78 8 3 4 Pin States in Power Save Modes 78 9 DISPLAY MEMORY INTERFACE 79 ...

Page 13: ...Single Dual Monochrome Panel 42 Table 7 13 LCD Interface Timing 4 Bit Single Color Panel 45 Table 7 14 LCD Interface Timing 8 Bit Single Color Panels Format 2 8 Bit Dual Color Panels 47 Table 7 15 LCD Interface Timing 16 Bit Single Dual Color Panels 49 Table 7 16 LCD Interface Timing 8 Bit Single Color Panels Format 1 51 Table 8 1 Gray Shade Color Mode Selection 62 Table 8 2 LCD Data Width 63 Tabl...

Page 14: ...on Research and Development Vancouver Design Center S1D13503 Hardware Functional Specification X18A A 001 08 Issue Date 01 01 29 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 15: ...38 Figure 20 Write Data to Display Memory 39 Figure 21 Read Data From Display Memory 40 Figure 22 LCD Interface Timing Monochrome Panel 41 Figure 23 LCD Interface Timing 4 Bit Single Color Panel 44 Figure 24 LCD Interface Timing 8 Bit Single Color Panels Format 2 8 Bit Dual Color Panels 46 Figure 25 LCD Interface Timing 16 Bit Single Dual Color Panels 48 Figure 26 LCD Interface Timing 8 Bit Single...

Page 16: ...Table Architecture 75 Figure 41 256 Level Color Mode Look Up Table Architecture 76 Figure 42 8 Bit Mode 8K bytes SRAM 79 Figure 43 8 Bit Mode 16K bytes SRAM 79 Figure 44 8 Bit Mode 32K bytes SRAM 80 Figure 45 8 Bit Mode 40K bytes SRAM 80 Figure 46 8 Bit Mode 64K bytes SRAM 81 Figure 47 16 Bit Mode 16K bytes SRAM 81 Figure 48 16 Bit Mode 64K bytes SRAM 82 Figure 49 16 Bit Mode 128K bytes SRAM 82 Fi...

Page 17: ...mption speed and cost requirements The S1D13503 offers a flexible microprocessor interface and is pin compatible with the S1D13502 within the same package types e g the 13503D0A is pin compatible with the 13502 the 13503 is pin compatible with the 13502 The S1D13503 is capable of displaying a maximum of 16 levels of gray shade or 256 simultaneous colors In gray shade modes a 16x4 Look Up Table is ...

Page 18: ...AM data bus interface configurations display memory configurations 128k bytes using one 64Kx16 SRAM 128k bytes using two 64Kx8 SRAMs 64k bytes using two 32Kx8 SRAMs 40k bytes using one 8Kx8 and one 32Kx8 SRAM 32k bytes using one 32Kx8 SRAM 16k bytes using two 8Kx8 SRAMs 8k bytes using one 8Kx8 SRAM 2 3 Display Modes 1 bit per pixel black and white display mode 2 4 bits per pixel 4 16 level gray sh...

Page 19: ...bit single 8 bit data transfer 8 bit dual 4 bit data transfer for each half panel passive color LCD panels 4 bit single 4 bit data transfer 8 bit single 8 bit data transfer 8 bit dual 4 bit data transfer for each half panel 16 bit single 8 bit data transfer with external circuit 16 bit dual 8 bit data transfer with external circuit See Section 9 5 on page 85 for complete details 2 5 Power Manageme...

Page 20: ...owing block diagrams are shown without SRAM or LCD display Refer to the interface specific Application Notes for complete details 3 1 16 Bit MC68000 MPU Figure 1 16 Bit 68000 Series example implementation only actual may vary S1D13503 MEMCS IOCS MC68000 DTACK D0 to D15 A1 to A19 AB1 to AB19 DB0 to DB15 IOW IOR Decoder AS R W BHE UDS READY A20 to A23 AB0 LDS Decoder A14 to A16 A10 to A19 FC0 to FC1...

Page 21: ...tual may vary MEMCS MEMW MEMR READY DB0 to DB7 AB0 to AB15 IOCS IOW IOR RESET S1D13503 Z80 RESET D0 to D7 WAIT A0 to A15 WR RD Decoder IORQ A10 to A15 Decoder MREQ MI 8086 Maximum mode CLK READY RESET RDY MEMW MEMR READY DB0 to DB15 AB0 to AB15 IOW IOR RESET S1D13503 8284A D0 to D15 T OE CLK S2 S1 S0 DEN MRDC AMWC IORC AIOWC DT R CLK READY RESET 8288 AB16 to AB19 M IO BHE A0 to A16 STB Decoder A16...

Page 22: ... SMEMW SMEMR IOCHRDY REFRESH SA0 to SA19 SD0 to SD7 DB0 to DB7 AB0 to AB19 Decoder SA16 to SA13 IOCS IOW IOR RESET RESET SA10 to SA15 AEN IOW IOR Decoder 0WS optional Decoder SA 1 or 4 through SA9 S1D13503 MEMCS MEMW MEMR READY 16 bit ISA Bus SMEMW SMEMR IOCHRDY REFRESH SA0 to SA19 SD0 to SD15 DB0 to DB15 AB0 to AB19 Decoder IOCS IOW IOR RESET RESET Decoder SA10 to SA15 AEN IOW IOR IOCS16 SA 1 or ...

Page 23: ...n internal index register 3 5 3 Sequence Controller The Sequence Controller generates horizontal and vertical display timings according to the configuration registers settings 3 5 4 LCD Panel Interface The LCD Panel Interface performs frame rate modulation and output data pattern formatting for both passive monochrome and passive color LCD panels Bus Control Registers Signal Translation Port Memor...

Page 24: ...Conversion maps the external data bus either 8 bit or 16 bit into the internal odd and even data bus 3 5 9 Address Generator The Address Generator generates display refresh addresses to be used to access display memory 3 5 10 MPU CRT Selector The MPU CRT Selector grants access to the display memory from either the MPU or the display refresh circuitry 3 5 11 Display Data Formatter The Display Data ...

Page 25: ...8 47 46 31 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DB6 DB5 DB4 DB3 DB2 DB1 DB0 OSC2 OSC1 BHE READY MEMR MEMW MEMCS IOR IOW IOCS VOE LCDENB XSCL AB19 VA0 VA1 VA2 VA3 VA4 VA5 VA6 VA7 VA8 VA9 VA10 VD0 VD1 VD2 VD3 VD4 VD5 VD6 S1D13503F00A DB7 V SS V DD DB8 DB9 DB10 DB11 DB12 DB13 DB15...

Page 26: ...6 31 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DB6 DB5 DB4 DB3 DB2 DB1 DB0 OSC2 OSC1 BHE READY MEMR MEMW MEMCS IOR IOW IOCS VOE LCDENB XSCL AB19 VA0 VA1 VA2 VA3 VA4 VA5 VA6 VA7 VA8 VA9 VA10 VD0 VD1 VD2 VD3 VD4 VD5 VD6 S1D13503F01A DB7 VDD VSS DB8 DB9 DB10 DB11 DB12 DB13 DB15 AB0 AB1...

Page 27: ... AB11 AB12 AB13 DB14 AB14 AB15 AB16 AB17 AB18 AB19 VA0 VA1 VA2 VA3 VA4 VA5 VA6 VA7 VA8 VA9 VA10 VD0 VD1 VD2 VD3 VD4 VD5 VD6 RESET WF XSCL2 LP YD LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 VCS1 VCS0 VWE VA15 VA14 VA13 VA12 VA11 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8 V DD V SS VD7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 OSC2 OSC1 BHE READY MEMR MEMW MEMCS IOR IOW IOCS VOE LCDENB XSCL 1 10 20 30 40 50 60 70 80 90 100 Dummy ...

Page 28: ...0 0 063 14 AB1 0 317 2 390 50 2 390 0 190 15 AB2 0 190 2 390 51 VA9 2 390 0 317 16 AB3 0 063 2 390 52 VA10 2 390 0 444 17 AB4 0 063 2 390 53 2 390 0 573 18 AB5 0 190 2 390 54 VD0 2 390 0 703 19 AB6 0 317 2 390 55 VD1 2 390 0 835 20 AB7 0 444 2 390 56 2 390 0 969 21 0 573 2 390 57 VD2 2 390 1 106 22 AB8 0 703 2 390 58 VD3 2 390 1 246 23 AB9 0 835 2 390 59 VD4 2 390 1 388 24 AB10 0 969 2 390 60 VD5 ...

Page 29: ...573 2 390 114 2 390 0 190 86 UD3 0 703 2 390 115 OSC1 2 390 0 317 87 UD2 0 835 2 390 116 OSC2 2 390 0 444 88 UD1 0 969 2 390 117 2 390 0 573 89 UD0 1 106 2 390 118 DB0 2 390 0 703 90 LD3 1 246 2 390 119 DB1 2 390 0 835 91 LD2 1 388 2 390 120 2 390 0 969 92 LD1 1 535 2 390 121 DB2 2 390 1 106 93 LD0 1 685 2 390 122 DB3 2 390 1 246 94 YD 1 840 2 390 123 DB4 2 390 1 388 95 2 000 2 390 124 DB5 2 390 1...

Page 30: ...ee Table 6 3 Input Specifications on page 27 TTLS TTL level input with hysteresis Table 5 1 Bus Interface Pin Name Type F00A Pin F01A Pin D00A Pad Driver Description DB0 DB15 I O 94 100 1 4 11 91 98 1 8 118 119 121 125 128 4 11 TS2 These pins are connected to the system data bus In 8 bit bus mode DB8 DB15 must be tied to VDD AB0 I 12 9 13 TTLS In MC68000 MPU interface this pin is connected to the ...

Page 31: ...CS I 87 84 107 TTLS Active low input to indicate a memory cycle MEMW I 88 85 109 TTLS Active low input to indicate a memory write cycle This pin should be tied to VDD in an MC68000 MPU interface MEMR I 89 86 110 TTLS Active low input to indicate a memory read cycle This pin should be tied to VDD in an MC68000 MPU interface READY O 90 87 112 TS3 For MC68000 MPU interface this pin is connected to th...

Page 32: ...p to configure various hardware options see Section Table 5 6 on page 26 VD0 VD15 each have an internal pull down resistor see Section Table 6 3 on page 27 VA0 VA15 O 33 43 62 66 30 40 59 63 38 40 42 43 45 46 48 49 51 52 77 81 CO1 These pins are connected to the display memory address bus VCS1 O 69 66 84 CO1 Active low chip select output to the second or odd byte address SRAM See Display Memory In...

Page 33: ...ane BIAS signal This output toggles once every frame or as programmed in AUX 05 bits 7 2 YD FPFRAME O 78 75 94 CO3 Vertical scanning start pulse A logic 1 on this signal sampled by the LCD module on the falling edge of LP is used by the panel Y driver row driver to indicate the start of the vertical frame LCDENB O 82 79 101 CO2 LCD enable signal output It can be used externally to turn off the pan...

Page 34: ...ta bytes in 16 bit bus interface No byte swap of high and low data bytes in 16 bit bus interface VD12 VD4 Select I O mapping address bits 9 1 These nine bits are latched on power up and are compared to the MPU address bits 9 1 A valid I O cycle combined with a valid address will enable the internal I O decoder Therefore both types of I O mapping are limited to even address boundaries to determine ...

Page 35: ... VSS 0 V 2 7 3 0 3 3 5 0 5 5 V VIN Input Voltage VSS VDD V IOPR Operating Current fOSC 6 MHz 256 colors 4 5 5 0 11 mA TOPR Operating Temperature 40 25 85 C PTYP Typical Active Power Consumption fOSC 6 MHz 256 colors 13 5 16 5 55 mW Table 6 3 Input Specifications Symbol Parameter Condition Min Typ Max Units VIL Low Level Input Voltage VDD 4 5V VDD 3 0V VDD 2 7V 0 8 0 4 0 3 V VIH High Level Input Vo...

Page 36: ...n IOL 2 mA IOL 4 mA IOL 6 mA 0 3 V VOL 3 0V Low Level Output Voltage Type 1 TS1D2 CO1 Type 2 TS2 CO2 Type 3 TS3 CO3 CO3S VDD Min IOL 1 8 mA IOL 3 5 mA IOL 5 mA 0 3 V VOH 5 0V High Level Output Voltage Type 1 TS1D2 CO1 Type 2 TS2 CO2 Type 3 TS3 CO3 CO3S VDD Min IOH 4 mA IOH 8mA IOH 12 mA VDD 0 4 V VOH 3 3V Low Level Output Voltage Type 1 TS1D2 CO1 Type 2 TS2 CO2 Type 3 TS3 CO3 CO3S VDD Min IOL 2 mA...

Page 37: ...imum 16MHz MPU clock IOW Timing Figure 10 IOW Timing MC68000 Table 7 1 IOW Timing MC68000 3V 3 3V 5V Symbol Parameter Min Max Min Max Units t1 AB 9 1 valid before AS falling edge 10 0 ns t2 AB 9 1 hold from AS rising edge 20 10 ns t3 IOCS hold from AS rising edge 0 0 ns t4 UDS LDS valid before AS rising edge 30 20 ns t5 UDS LDS falling edge to DTACK falling edge 40 25 ns t6 AS rising edge to DTACK...

Page 38: ...efore AS falling edge 10 0 ns t2 AB 9 1 and IOCS hold from AS rising edge 20 10 ns t3 AS falling edge to DTACK falling edge 40 25 ns t4 AS rising edge to DTACK hi z delay 40 25 ns t5 AS falling edge to DB 15 0 valid 60 40 ns t6 DB 15 0 hold from AS rising edge 20 15 ns t7 AS rising edge to DB 15 0 hi z delay 35 25 ns AB 9 1 AS R W VALID VALID t2a t3 t7 t1 DB 15 0 IOCS UDS LDS t4 t5 t6 DTACK Hi Z H...

Page 39: ...3 3V 5V Symbol Parameter Min Max Min Max Units t1 AB 19 1 and MEMCS valid before AS falling edge 0 0 ns t2 AB 19 1 and MEMCS hold from AS rising edge 0 0 ns t3 AS falling edge to DTACK falling edge 3 5 MCLK 20 3 5 MCLK 10 ns t4 AS rising edge to DTACK hi z delay 40 25 ns t5 AS falling edge to DB 15 0 valid MCLK 40 MCLK 20 ns t6 DB 15 0 hold from AS rising edge 0 0 ns AB 19 1 AS UDS LDS VALID VALID...

Page 40: ...r Min Max Min Max Units t1 AB 19 1 and MEMCS valid before AS falling edge 0 0 ns t2 AB 19 1 and MEMCS hold from AS rising edge 0 0 ns t3 AS falling edge to DTACK falling edge 3 5 MCLK 20 3 5 MCLK 10 ns t4 AS rising edge to DTACK hi z delay 40 15 ns t5 DTACK falling edge to DB 15 0 valid 20 15 ns t6 DB 15 0 hold from AS rising edge 25 15 ns t7 AS rising edge to DB 15 0 hi z delay 40 30 ns AB 19 1 A...

Page 41: ...7 5 IOW Timing Non MC68000 3V 3 3V 5V Symbol Parameter Min Max Min Max Units t1 AB 9 0 BHE and IOCS valid before IOW falling edge 10 0 ns t2 AB 9 0 BHE and IOCS hold from IOW rising edge 20 10 ns t3 DB 15 0 setup to IOW rising edge 20 10 ns t4 DB 15 0 hold from IOW rising edge 20 10 ns t5 Pulse width of IOW 30 20 ns AB 9 0 IOCS IOW VALID VALID t2 t4 t3 t1 DB 15 0 BHE t5 Hi Z Hi Z Downloaded from E...

Page 42: ...V Symbol Parameter Min Max Min Max Units t1 AB 9 0 BHE and IOCS valid before IOR falling edge 10 0 ns t2 AB 9 0 BHE and IOCS hold from IOR rising edge 20 10 ns t3 IOR falling edge to DB 15 0 valid 60 40 ns t4 DB 15 0 hold from IOR rising edge 20 15 ns t5 IOR rising edge to DB 15 0 hi z delay 35 25 ns AB 9 0 IOCS IOR VALID VALID t2 t4 t5 t3 t1 DB 15 0 BHE Hi Z Hi Z Downloaded from Elcodis com elect...

Page 43: ...000 3V 3 3V 5V Symbol Parameter Min Max Min Max Units t1 AB 19 0 BHE and MEMCS valid before MEMW falling edge 0 0 ns t2 AB 19 0 BHE and MEMCS hold from MEMW rising edge 0 0 ns t3 MEMW falling edge to READY falling edge 30 20 ns t4 MEMW falling edge to DB 15 0 valid MCLK 40 MCLK 20 ns t5 DB 15 0 hold from MEMW rising edge 0 0 ns t6 READY negated pulse width 3 5 MCLK 20 3 5 MCLK 10 ns AB 19 0 MEMCS ...

Page 44: ...arameter Min Max Min Max Units t1 AB 19 0 BHE and MEMCS valid before MEMR falling edge 0 0 ns t2 AB 19 0 BHE and MEMCS hold from MEMR rising edge 0 0 ns t3 MEMR falling edge to READY falling edge 30 20 ns t4 READY rising edge to DB 15 0 valid 15 10 ns t5 DB 15 0 hold from MEMR rising edge 20 10 ns t6 MEMR rising edge to DB 15 0 hi z delay 30 20 ns t7 READY negated pulse width 3 5 MCLK 20 3 5 MCLK ...

Page 45: ...ts Table 7 9 Clock Input Requirements Symbol Parameter Min Typ Max Units TOSC Input Clock Period CLKI 40 ns tPWH Input Clock Pulse Width High CLKI 40 60 TOSC tPWL Input Clock Pulse Width Low CLKI 40 60 TOSC tf Input Clock Fall Time 10 90 5 ns tr Input Clock Rise Time 10 90 5 ns t PWL t PWH t f Clock Input Waveform t r T OSC V IH V IL 10 90 Downloaded from Elcodis com electronic components distribu...

Page 46: ...e Rate Calculation on page 84 The crystal oscillator must be fundamental mode and have the following recommended RC load values RL 2MΩ 5 CL 6 8 pF The figure below demonstrates both a crystal interface and an oscillator interface to the S1D13503 Figure 19 Recommended Clock Interface S1D13503 92 93 RL X1 CL CL S1D13503 92 93 OUT GND VCC NC VCC Crystal Interface Oscillator Interface X1 Downloaded fr...

Page 47: ... and 9 3 Table 7 10 Write Data to Display Memory 3V 3 3V 5V Symbol Parameter Min Max Min Max Units t1 Address cycle time MCLK 15 MCLK 10 ns t2 VA 15 0 VCS0 and VCS1 valid before VWE falling edge 0 0 ns t3 VA 15 0 VCS0 and VCS1 hold from VWE rising edge 0 0 ns t4 Pulse width of VWE MCLK 15 MCLK 10 ns t5 VD 15 0 setup to VWE rising edge MCLK 20 MCLK 15 ns t6 VD 15 0 hold from VWE rising edge 0 0 ns ...

Page 48: ... period 1 fOSC or 2 fOSC or 4 fOSC depending on which display mode the chip is in See section 9 2 and 9 3 Table 7 11 Read Data From Display Memory 3V 3 3V 5V Symbol Parameter Min Max Min Max t1 Address cycle time MCLK 15 MCLK 10 t2 VA 15 0 VCS0 and VCS1 access time MCLK 40 MCLK 25 t3 VD 15 0 hold time 0 0 VA 15 0 VCS0 VCS1 INPUT INPUT INPUT t1 t2 t3 VD 15 0 VALID Downloaded from Elcodis com electr...

Page 49: ...ing 4 Bit Single 8 Bit Single Dual Monochrome Panels Figure 22 LCD Interface Timing Monochrome Panel YD S1D13503 outputs t1 t2 t4 t3 LP WF LP XSCL AUX 01 bit 5 0 XSCL AUX 01 bit 5 1 t7a t8 t9 t5 t6a t10 t12 t11 UD 3 0 LD 3 0 t13 t7b t8 t9 t10 t11 UD 3 0 LD 3 0 t12 1 2 1 2 S1D13503 outputs t6b t6c 80 LP S1D13503 outputs Downloaded from Elcodis com electronic components distributor ...

Page 50: ...01 bit 5 1 and AUX 03 bit 2 0 13tOSC 5 15tOSC 5 ns t6b XSCL falling edge to LP falling edge single panel mode AUX 01 bit 5 1 and AUX 03 bit 2 1 12tOSC 5 13tOSC 5 ns t6c XSCL falling edge to LP falling edge dual panel mode AUX 01 bit 5 1 and AUX 03 bit 2 0 n a 31tOSC 5 ns t6c XSCL falling edge to LP falling edge dual panel mode AUX 01 bit 5 1 and AUX 03 bit 2 1 n a 29tOSC 5 ns t7a LP falling edge t...

Page 51: ...ails 10 ns for 5V operation 24 ns for 3 0V and 3 3V operation t11 UD 3 0 LD 3 0 setup to XSCL falling edge AUX 03 bit 2 1 tOSC 10 2tOSC 10 ns t12 UD 3 0 LD 3 0 hold from XSCL falling edge AUX 03 bit 2 0 2tOSC 10 4tOSC 10 ns t12 UD 3 0 LD 3 0 hold from XSCL falling edge AUX 03 bit 2 1 tOSC 10 2tOSC 10 ns t13 LP falling edge to XSCL rising edge AUX 01 bit 5 1 5tOSC 5 5tOSC 5 ns Table 7 12 LCD Interf...

Page 52: ...al Specification X18A A 001 08 Issue Date 01 01 29 7 4 2 LCD Interface Timing 4 Bit Single Color Panel Figure 23 LCD Interface Timing 4 Bit Single Color Panel t4 t1 LP t2 t3 t6 t13 t7 t10 t9 t8 1 2 3 t11 t12 YD LP XSCL UD 4 t5 WF Downloaded from Elcodis com electronic components distributor ...

Page 53: ...0 5tOSC 24 Symbol Parameter Min Typ Max Units t1 LP period HT HNDP 10 ns t2 YD hold from LP falling edge 13tOSC 10 ns t3 LP pulse width 5tOSC 5 ns t4 WF delay from LP falling edge 0 20 ns t5 LP setup to XSCL falling edge 19tOSC 5 ns t6 XSCL falling edge to LP falling edge 20tOSC 5 ns t7 LP falling edge to XSCL falling edge 14tOSC 5 ns t8 XSCL period tOSC 5 ns t9 XSCL high width 0 5tOSC 5 ns t10 XS...

Page 54: ... Date 01 01 29 7 4 3 LCD Interface Timing 8 Bit Single Color Panels Format 2 8 Bit Dual Color Panels Figure 24 LCD Interface Timing 8 Bit Single Color Panels Format 2 8 Bit Dual Color Panels t1 LP t2 t3 t6 t7 t5 t8 t10 t9 1 2 3 t12 t11 YD LP XSCL UD LD 4 t13 t4 WF Downloaded from Elcodis com electronic components distributor ...

Page 55: ...ingle panel mode HT HNDP 10 ns t1 LP period dual panel mode 2 HT HNDP 10 ns t2 YD hold from LP falling edge 13tOSC 10 ns t3 LP pulse width 5tOSC 5 ns t4 WF delay from LP falling edge 0 20 ns t5 LP setup to XSCL falling edge 19 5tOSC 5 ns t6 XSCL falling edge to LP falling edge single panel mode 20tOSC 5 ns t6 XSCL falling edge to LP falling edge dual panel mode 52tOSC 5 ns t7 LP falling edge to XS...

Page 56: ...ion X18A A 001 08 Issue Date 01 01 29 7 4 4 LCD Interface Timing 16 Bit Single Dual Color Panels Figure 25 LCD Interface Timing 16 Bit Single Dual Color Panels t1 LP t2 t3 t6 t13 t7 t10 t9 t8 1 2 3 t11 t12 YD LP XSCL UD LD 4 t5 t14 t15 WF t4 Downloaded from Elcodis com electronic components distributor ...

Page 57: ...2 HT HNDP 10 ns t2 YD hold from LP falling edge 13tOSC 10 ns t3 LP pulse width 5tOSC 5 ns t4 WF delay from LP falling edge 0 20 ns t5 LP setup to XSCL falling edge 22tOSC 5 ns t6 XSCL falling edge to LP falling edge single panel mode 20tOSC 5 ns t6 XSCL falling edge to LP falling edge dual panel mode 52tOSC 5 ns t7 LP falling edge to XSCL falling edge 17tOSC 5 ns t8 XSCL period 5tOSC 5 ns t9 XSCL ...

Page 58: ...ate 01 01 29 7 4 5 LCD Interface Timing 8 Bit Single Color Panels Format 1 Figure 26 LCD Interface Timing 8 Bit Single Color Panels Format 1 t1 LP t2 t3 t7a t14b t7b t8b t6b t9b t11b t10b t6a t14a t8a t11a t10a t9a 1 2 3 t13b t12a t13a t12b YD LP XSCL2 XSCL UD LD WF Downloaded from Elcodis com electronic components distributor ...

Page 59: ...SC 5 ns t6b LP setup to XSCL2 falling edge 19 5tOSC 5 ns t7a XSCL falling edge to LP falling edge 20tOSC 5 ns t7b XSCL2 falling edge to LP falling edge 23 5tOSC 5 ns t8a LP falling edge to XSCL falling edge 17tOSC 5 ns t8b LP falling edge to XSCL2 falling edge 14 5tOSC 5 ns t9a XSCL period 4tOSC 5 ns t9b XSCL2 period 4tOSC 5 ns t10a XSCL high width tOSC 5 ns t10b XSCL2 high width tOSC 5 ns t11a XS...

Page 60: ...e Options Figure 27 4 Bit Single Monochrome Panel Timing LP 240 PULSES LP XSCL UD 3 0 LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 YD LINE1 LINE2 LP 4 PULSES LP WF UD2 1 2 1 6 1 318 UD1 1 3 1 7 1 319 UD0 1 4 1 8 1 320 UD3 1 1 1 5 1 317 WF XSCL 80 CLOCK PERIODS Example Timing for a 320x240 single panel Downloaded from Elcodis com electronic components distributor ...

Page 61: ...ing LP 480 PULSES LP XSCL UD 3 0 LD 3 0 LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 YD LINE1 LINE2 LP WF UD2 1 2 1 10 1 634 UD1 1 3 1 11 1 635 UD0 1 4 1 12 1 636 LD3 1 5 1 13 1 637 LD2 1 6 1 14 1 638 LD1 1 7 1 15 1 639 LD0 1 8 1 16 1 640 UD3 1 1 1 9 1 633 WF LP 4 PULSES Example timing for a 640x480 panel XSCL 80 CLOCK PERIODS Downloaded from Elcodis com electronic components distributor ...

Page 62: ...D 3 0 LD 3 0 LINE1 241 LINE2 242 LINE3 243 LINE4 244 LINE 239 479 LINE240 480 YD LP WF UD2 1 2 1 6 1 638 UD1 1 3 1 7 1 639 UD0 1 4 1 8 1 640 LD3 241 1 241 5 241 637 LD2 241 638 LD1 241 639 LD0 241 640 UD3 1 1 1 5 1 637 XSCL 160 CLOCK PERIODS WF 241 2 241 6 241 3 241 7 241 4 241 8 LP 2 PULSES Example timing for a 640x480 panel LINE1 241 LINE2 242 Downloaded from Elcodis com electronic components di...

Page 63: ...t Single Color Panel Timing LP 240 PULSES LP XSCL UD 3 0 LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 YD LINE1 LINE2 LP UD2 1 G1 1 B2 1 R320 UD1 1 B1 1 R3 1 G320 UD0 1 R2 1 G3 1 B320 UD3 1 R1 1 G2 1 B319 XSCL 240 CLOCK PERIODS 1 R4 1 G4 1 B4 1 B3 Example timing for a 320x240 panel LP 4 PULSES WF WF Downloaded from Elcodis com electronic components distributor ...

Page 64: ...LINE4 LINE479 LINE1 LINE2 1 G1 1 R2 1 B2 1 G3 1 R4 1 B4 1 G5 1 R6 1 R636 1 B636 1 G637 1 R638 1 B638 1 G639 1 R640 1 B640 LD 3 0 1 G6 1 R7 1 B7 1 G8 1 R9 1 B9 1 G10 1 R11 1 R12 1 B12 1 G13 1 R14 1 B14 1 G15 1 R16 1 B16 1 B6 1 G7 1 R8 1 B8 1 G9 1 R10 1 B10 1 G11 1 B11 1 G12 1 R13 1 B13 1 G14 1 R15 1 B15 1 G16 1 B635 1 G636 1 R637 1 B637 1 G638 1 R639 1 B639 1 G640 1 R1 1 B1 1 G2 1 R3 1 B3 1 G4 1 R5...

Page 65: ... PULSES LP XSCL LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 YD LINE1 LINE2 LP UD2 1 G1 1 R4 1 B318 UD1 1 B1 1 G4 UD0 1 R2 1 B4 1 G319 UD3 1 R1 1 B3 1 G318 XSCL 120 CLOCK PERIODS 1 B6 1 R7 1 G7 1 G6 1 B2 1 G5 1 R320 1 R3 1 B5 1 G320 1 G3 1 R6 1 B320 1 G2 1 R5 1 B319 1 R8 1 G8 1 B8 1 B7 LD3 LD2 LD1 LD0 1 R319 Example timing for a 320x240 panel LD 3 0 UD 3 0 LP 4 PULSES WF WF Downloaded from Elcodis com ...

Page 66: ...E242 241 G1 241 B1 241 R2 241 B3 241 R4 241 G4 241 B4 LD 3 0 LINE1 LINE240 LINE2 LINE3 LINE4 LINE239 LINE1 LINE2 241 G2 241 B2 241 R3 241 G3 1 R637 1 G637 1 B637 1 R638 1 B639 1 R640 1 G640 1 B640 1 G638 1 B638 1 R639 1 G639 1 R1 1 G1 1 B1 1 R2 1 B3 1 R4 1 G4 1 B4 1 G2 1 B2 1 R3 1 G3 241 R637 241 G637 241 B637 241 R638 241 B639 241 R640 241 G640 241 B640 241 G638 241 B638 241 R639 241 G639 Example...

Page 67: ... UD5 UD4 UD7 LD3 LD2 LD1 LD0 1 G1 1 R4 1 R2 1 B4 1 B2 1 G5 1 G3 1 R6 LD6 LD5 LD4 LD7 1 B3 1 G4 1 R5 1 B5 UD3 UD2 UD1 UD0 1 R4 1 B4 1 G5 1 R6 LD3 LD2 LD1 LD0 16 BIT PANEL INPUTS 1 R1 1 B1 1 G2 1 R3 1 B635 1 G636 1 R637 1 B637 1 B638 1 G639 1 R640 1 B640 1 G638 1 R639 1 B639 1 G640 1 G1 1 R2 1 B2 1 G3 1 R636 1 B636 1 G637 1 R638 1 G638 1 R639 1 B639 1 G640 1 B638 1 G639 1 R640 1 B640 1 R636 1 B636 1...

Page 68: ...L INPUTS 1 R1 1 G1 1 B1 1 R2 1 G638 1 B638 1 R639 1 G639 241 B639 1 B639 1 R640 1 G640 1 B640 241 R1 241 G638 1 B639 1 R640 1 G640 1 B640 241 B639 1 G2 1 R4 1 G4 1 B4 1 G638 1 B638 1 R639 1 G639 241 G2 241 B3 241 G1 241 B2 241 R4 241 B1 241 R3 241 B4 241 R2 241 G3 241 B4 241 G638 241 R640 241 B638 241 G640 241 R639 241 B640 241 G639 241 G1 241 B1 241 R2 241 G2 241 B2 241 R3 241 G3 241 B638 241 R63...

Page 69: ...rite data IOW I O mapped address 1 data write data to the indexed register or read data IOR I O mapped address 1 read the indexed register To perform a 16 bit I O access write data IOW I O mapped address index data write the index and data of the register to be accessed read data IOW I O mapped address index write to the indexed register IOR I O mapped address 1 read the indexed register 8 1 Regis...

Page 70: ... this pin can be used as a general I O pin if desired When LCDE 0 LCDENB is forced low When LCDE 1 LCDENB is forced high LCDE goes low on RESET bit 3 Gray Shade Color In gray shade display modes this bit selects between 16 level or 4 level gray shade display When this bit 1 16 gray shades are displayed 4 bits pixel When this bit 0 4 gray shades of a possible 16 are dis played 2 bits pixel In color...

Page 71: ...ay memory data bus interface is selected This bit goes low on RESET This bit is ignored for a 16 bit memory interface bits 7 0 Line Byte Count Bits 7 0 Along with Line Byte Count Bit 8 AUX 03 bit 0 this is the number of bytes to be fetched per display line minus 1 To calculate the Line Byte Count use the following formula Example To calculate the Line Byte Count for 640 horizontal pixels with 16 g...

Page 72: ... BW display mode the Look Up Table is always bypassed and in color display mode the Look Up Table cannot be bypassed The LUT Bypass bit goes low on RESET Table 8 3 Maximum Value of Line Byte Count Register 8 Bit Display Memory Interface Display Modes Maximum Value of Line Byte Count Register Corresponding Maximum Number of Pixels in One Display Line black and white BW 0FFh 256 x 8 2048 4 level gra...

Page 73: ...tails This bit goes low on RESET bit 0 Line Byte Count Bit 8 This is the MSB of the number of bytes to be fetched per display line minus 1 see AUX 02 This bit only has effect when in either 16 colors gray shades with 8 bit memory interface or 256 colors with 16 bit memory interface bits 7 0 Total Display Line Count Bits 7 0 These are the 8 LSB of the 10 bit Total Display Line Count and represent t...

Page 74: ...n screen 1 refers to the upper half of the display While in a single panel configuration screen 1 refers to the first screen of the Split Screen Display feature where two differ ent images screen 1 and screen 2 can be displayed at the same time on one display Note The absolute address into display memory is determined by the Memory Mapping Address which is set by VD13 VD15 see Table 5 6 Summary of...

Page 75: ...n be displayed at the same time on one display The Screen 2 Display Start Address is the memory address corresponding to the first pixel of the second image stored in display memory To display screen 2 refer to AUX 0A Screen 1 Display Line Count Register LSB on page 68 AUX 08 Screen 2 Display Start Address Register LSB I O address 1000b Read Write Screen 2 Display Start Addr Bit 7 Screen 2 Display...

Page 76: ...isters AUX 06 and AUX 07 and 240 33 207 lines will be displayed on the lower part of the screen as dictated by the screen 2 display start address registers AUX 08 and AUX 09 Two different images can be displayed when using a dual panel configuration by changing the screen 2 dis play start address However by using this method screen 2 is limited to the lower half of the display This register is ign...

Page 77: ...d If the output display size is 320x240 then the whole image can be seen by changing display starting addresses through AUX 06 and 07 and AUX 08 and 09 Note that a virtual screen can be produced on either a single or dual panel In 8 bit memory interface if the Address Pitch Adjustment is not equal to zero a virtual screen with a line length of Line Byte Count AUX 0D bytes is created with the displ...

Page 78: ...he display of green colors Only bit 0 of these two bits controls which bank is currently selected bits 5 4 ID Bit RGB Index Bits 1 0 These bits have dual purpose ID Bits After power on or hardware reset these bits can be read to identify the S1D13503 These same bits are used to identify the pin compatible S1D13502 and would only be used in system implementations where common software is being used...

Page 79: ...is arranged into two 8 position banks for the display of red colors Only bit 0 of these two bits controls which bank is currently selected These bits have no effect in all gray shade or 16 color display modes bit 5 4 Blue Bank Bits 1 0 In both the 4 and 256 color display modes the 16 position Blue palette is arranged into four 4 position banks for the display of blue colors These two bits control ...

Page 80: ...k of 16 4 color 4 banks of 4 4 banks of 4 4 banks of 4 16 color 1 bank of 16 1 bank of 16 1 bank of 16 256 color 2 banks of 8 2 banks of 8 4 banks of 4 Indicates the palette is not used for that display mode Green Look Up Table 0 1 2 3 2 bit pixel data 0 1 2 3 0 1 2 3 0 1 2 3 Bank 0 Bank 1 Bank 2 Bank 3 Bank Select bits 1 0 Aux 0E bits 7 6 4 bit display data output Bank Select Logic Note the above...

Page 81: ... 001 08 16 Level Gray Shade Mode Figure 38 16 Level Gray Shade Mode Look Up Table Architecture Note The Look Up Table is bypassed in black and white display mode 4 bit pixel data P3 P2 P1 P0 4 bit Look Up Table data output msb lsb Green Look Up Table 16x4 0 1 2 3 C D E F Downloaded from Elcodis com electronic components distributor ...

Page 82: ...k 3 Red Bank Select bits 1 0 Aux 0F bits 7 6 Bank Select Logic 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 Bank 0 Bank 1 Bank 2 Bank 3 Green Bank Select bits 1 0 Aux 0E bits 7 6 Bank Select Logic 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 Bank 0 Bank 1 Bank 2 Bank 3 Blue Bank Select bits 1 0 Aux 0F bits 5 4 Bank Select Logic RED Look Up Table GREEN Look Up Table Blue Look Up Table 4 bit GREEN 4 bit RED display data outp...

Page 83: ...gure 40 16 Level Color Mode Look Up Table Architecture 4 bit pixel data 4 bit RED Look Up Table data output Red Look Up Table 16x4 0 1 2 3 C D E F 4 bit GREEN Look Up Table data output Green Look Up Table 16x4 0 1 2 3 C D E F 4 bit BLUE Look Up Table data output Blue Look Up Table 16x4 0 1 2 3 C D E F Downloaded from Elcodis com electronic components distributor ...

Page 84: ...0 1 2 3 4 5 6 7 Bank 1 Bank Select Logic 3 bit pixel data 0 1 2 3 2 bit pixel data 0 1 2 3 0 1 2 3 0 1 2 3 Bank 0 Bank 1 Bank 2 Bank 3 Blue Bank Select bits 1 0 Aux 0F bits 5 4 Bank Select Logic Blue Look Up Table Green Look Up Table Green Bank Select bit Aux 0E bit 6 Red Bank Select bit Aux 0F bit 6 7 6 5 4 3 2 1 0 R2 R1 R0 G2 G1 G0 B1 B0 256 Color Data Format 4 bit GREEN 4 bit RED display data o...

Page 85: ...terface and the number of Gray shades State 1 I O read write of all registers allowed Memory read write allowed LCD outputs are either forced low AUX 03 bit 5 0 or high impedance AUX 03 bit 5 1 State 2 The same as State 1 as well as Master clock for display memory access is disabled Once a valid memory read write cycle is detected the S1D13503 returns to State 1 where the MPU access is serviced Th...

Page 86: ... Access Possible Yes Yes Yes Yes Memory Access Possible Yes Yes No No Sequence Controller Running Yes No No No Internal Oscillator Disabled No No No Yes Table 8 11 Pin States in Power Save Modes Pin Pin State Normal Active PSM1 PSM2 State 1 State 2 UD 3 0 LD 3 0 LP XSCL YD WF XSCL2 Note 1 Active High Impedance High Impedance High Impedance UD 3 0 LD 3 0 LP XSCL YD WF XSCL2 Note 2 Active Forced Low...

Page 87: ... DISPLAY MEMORY INTERFACE 9 1 SRAM Configurations Supported 9 1 1 8 Bit Mode Figure 42 8 Bit Mode 8K bytes SRAM Figure 43 8 Bit Mode 16K bytes SRAM Requires AUX 01 bit 0 0 8Kx8 S1D13503 VWE VD0 7 VCS0 VCS1 VA0 12 WE CS n c 8Kx8 S1D13503 VWE VD0 7 VCS0 VCS1 VA0 12 WE CS 8Kx8 WE CS Downloaded from Elcodis com electronic components distributor ...

Page 88: ...4 8 Bit Mode 32K bytes SRAM Requires AUX 01 bit 0 1 Figure 45 8 Bit Mode 40K bytes SRAM either 8Kx8 32Kx8 requiring AUX 01 bit 0 0 or 32Kx8 8Kx8 requiring AUX 01 bit 0 1 32Kx8 S1D13503 VWE VD0 7 VCS0 VCS1 VA0 14 WE CS n c 8K 32Kx8 S1D13503 VWE VD0 7 VCS0 VCS1 VA0 14 WE CS 32K 8Kx8 WE CS Downloaded from Elcodis com electronic components distributor ...

Page 89: ...01 29 X18A A 001 08 Figure 46 8 Bit Mode 64K bytes SRAM Requires AUX 01 bit 0 1 9 1 2 16 bit Mode Figure 47 16 Bit Mode 16K bytes SRAM 32Kx8 S1D13503 VWE VD0 7 VCS0 VCS1 VA0 14 WE CS 32Kx8 WE CS S1D13503 VWE VD0 7 VD8 15 VCS0 VCS1 VA0 12 8Kx8 WE CS 8Kx8 CS WE Downloaded from Elcodis com electronic components distributor ...

Page 90: ...8A A 001 08 Issue Date 01 01 29 Figure 48 16 Bit Mode 64K bytes SRAM Figure 49 16 Bit Mode 128K bytes SRAM S1D13503 VWE VD0 7 VD8 15 VCS0 VCS1 VA0 14 32Kx8 WE CS 32Kx8 CS WE S1D13503 VWE VD0 7 VD8 15 VCS0 VCS1 VA0 15 WE UB LB A0 15 I O 1 8 I O 9 16 Downloaded from Elcodis com electronic components distributor ...

Page 91: ...25ns 4 level gray shades 4 level colors Access time 2 fOSC 40ns Access time 2 fOSC 25ns Black and White BW Access time 2 fOSC 40ns Access time 2 fOSC 25ns Table 9 2 16 Bit Display Memory Interface SRAM Access Time Display Mode 3V 3 3V 5V 256 level colors Access time 1 fOSC 40ns Access time 1 fOSC 25ns 16 level gray shades 16 level colors Access time 2 fOSC 40ns Access time 2 fOSC 25ns 4 level gray...

Page 92: ...nel in gray shade display modes and DHNDP 32 pixels per panel in BW display mode and in color display modes Where PHNDP is Programmable Horizontal Non Display Period in term of pixels PHNDP 0 pixels when AUX 0C 0 and PHNDP pixels when AUX 0C not equal to zero FrameRate 2 f osc HorizontalPixels PHNDP DHNDP VerticalLines 4 FrameRate fosc HorizontalPixels PHNDP DHNDP VerticalLines 4 FrameRate 2 f osc...

Page 93: ...ode Black and White BW 1 bit per pixel 4 Grays 4 Colors 2 bits per pixel 16 Grays 16 Colors 4 bits per pixel 256 Colors 8 bits per pixel Condition AUX 0C AUX 02 AUX 0C 0 AUX 0C 0 AUX 0C 0 Example Display Memory Interface Size Access Time Size Access Time Size Access Time Size Access Time Input Clock fOSC Frame Rate KB 3V 3 3V 5V KB 3V 3 3V 5V KB 3V 3 3V 5V KB 3V 3 3V 5V BW Gray Color 480 8 bit 16 ...

Page 94: ...5 ns 29 210 ns 460 ns 225 ns 475 ns 57 85 ns 210 ns 100 ns 225 ns 113 2 3 85 ns 2 3 100 ns 8 MHz 66 Hz 64 Hz 200 8 bit 16 bit 12 210 ns 460 ns 225 ns 475 ns 23 5 210 ns 460 ns 225 ns 475 ns 47 85 ns 210 ns 100 ns 225 ns 94 2 3 85 ns 2 3 100 ns 8 MHz 79 Hz 77 Hz Number of Horizontal Pixels 320 Display Mode Black and White BW 1 bit per pixel 4 Grays 4 Colors 2 bits per pixel 16 Grays 16 Colors 4 bit...

Page 95: ... 01 29 X18A A 001 08 10 MECHANICAL DATA Figure 50 Mechanical Drawing QFP5 100 S2 S1D13503F00A 0 65 0 1 0 30 0 1 1 6 0 8 0 1 23 2 0 04 20 0 0 1 14 0 0 1 17 2 0 04 0 12 0 15 0 05 2 7 0 1 Index 100 1 30 31 50 51 80 81 QFP5 100PIN S2 S1D13503 All dimensions in mm Downloaded from Elcodis com electronic components distributor ...

Page 96: ...8A A 001 08 Issue Date 01 01 29 Figure 51 Mechanical Drawing QFP15 100 STD S1D13503F01A QFP15 100PIN STD 1 25 75 51 50 26 76 100 Index 0 12 14 0 0 1 14 0 0 1 16 0 0 4 16 0 0 4 0 168 0 1 0 5 1 4 0 1 0 125 0 1 0 5 0 2 S1D13503 1 All dimensions in mm Downloaded from Elcodis com electronic components distributor ...

Page 97: ...e in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other tradem...

Page 98: ...pson Research and Development Vancouver Design Center S1D13503 Programming Notes and Examples X18A G 002 06 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 99: ...3 2 5 Four Colors Two Bits Pixel in Color Mode 28 3 2 6 Sixteen Gray Shades Four Bits Pixel in Monochrome Mode 30 3 2 7 Sixteen Colors Four Bits Pixel in Color Mode 31 3 2 8 256 Colors Eight Bits Pixel in Color Mode 32 4 DISPLAY MEMORY MODELS 34 4 1 Registers 34 4 2 Description 36 4 2 1 S5U13503B00C Evaluation Board Display Memory 36 4 2 2 Display Start Address Registers 37 4 3 Common Display Memo...

Page 100: ...A G 002 06 Issue Date 01 01 30 5 6 Power Saving 54 5 6 1 Registers 54 5 6 2 Power Save Modes 54 6 IDENTIFYING THE S1D13503 56 7 PROGRAMMING THE S1D13503 57 7 1 Main Loop Code 58 7 2 Initialization Code 60 7 3 Advanced Functions 66 8 GLOSSARY 88 Downloaded from Elcodis com electronic components distributor ...

Page 101: ...S1D13503 Inverted Look Up Table White To Black 25 Table 3 8 S1D13503 Black To White Look up Table For 4 Gray Shades 26 Table 3 9 S1D13503 Low To High Intensity Color Look Up Table For 4 Colors 28 Table 3 10 Simulation Of First 16 Entries Of Standard VGA Palette 31 Table 3 11 Examples Of 256 Pixel Colors Using Linear LUT 32 Table 4 1 Memory Size Requirements 38 Table 5 1 Smallest Number Of Pixels F...

Page 102: ...pson Research and Development Vancouver Design Center S1D13503 Programming Notes and Examples X18A G 002 06 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 103: ...Table Architecture 30 Figure 8 16 Level Color Mode Look Up Table Architecture 31 Figure 9 256 Level Color Mode Look Up Table Architecture 33 Figure 10 Memory Map Example For 320 x 240 LCD Panel With 4 Colors Gray Shades 38 Figure 11 Memory Map Example For 320 x 240 LCD Panel With 256 Colors 39 Figure 12 Memory Map Example For 640 x 200 LCD Panel With 16 Colors Gray Shades 39 Figure 13 Moving A Vie...

Page 104: ...pson Research and Development Vancouver Design Center S1D13503 Programming Notes and Examples X18A G 002 06 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 105: ... LCD controller with reference made to the S5U13503B00C evaluation board The first half of this guide presents the basic concepts of LCD controllers The second half of this guide presents programming examples which are combined in a simple menu driven program Most of the program is written in the C programming language with some parts written in 8086 assembly Downloaded from Elcodis com electronic...

Page 106: ...001 b7 display off application specific the recommended procedure is to turn this bit off during register initialization and afterwards turn this bit on b6 single panel panel specific b5 XSCL is masked panel specific b4 LCDE LCDENB pin set to disable specific power supply design for S5U13503B00C set bit to 0 to disable power supply application specific the recommended procedure is to disable the p...

Page 107: ... Line Count bits 9 8 of Screen 1 Display Line Count in bits 1 0 of AUX 0Bh Screen 1 Display Line Count is typically the same as Total Display Line Count AUX 0Ah AUX 04h bits 1 0 of AUX 0Bh bits 1 0 of AUX 05h see Section 5 4 Split Screen on page 45 AUX 0Bh 0000 0000 bits 7 2 don t care recommend clearing bits bits 1 0 bits 9 8 of Screen 1 Display Line Count application specific see AUX 0Ah AUX 0Ch...

Page 108: ...e address AUX 0Fh 0000 1101 write Red data AUX 0Fh 0000 1101 write Green data AUX 0Fh 0000 0101 write Blue data AUX 0Eh 0000 0111 increment palette address AUX 0Fh 0000 1111 write Red data AUX 0Fh 0000 1111 write Green data AUX 0Fh 0000 0000 write Blue data AUX 0Eh 0000 1000 increment palette address AUX 0Fh 0000 1111 write Red data AUX 0Fh 0000 1111 write Green data AUX 0Fh 0000 0001 write Blue d...

Page 109: ...01 0000b OR original value for AUX 01h b7 display on application specific b4 LCDE LCDENB pin set to enable specific power supply design for S5U13503B00C set bit to 1 to enable power supply application specific Write one pixel to the top left corner of display memory If the S5U13503B00C evaluation board is used in indexed I O mode there are two video memory banks which begin at D000 0000 2 banks x ...

Page 110: ...ic b5 XSCL not masked panel specific b4 LCDE LCDENB pin set to disable specific power supply design for S5U13503B00C set bit to 0 to disable power supply application specific the recommended procedure is to disable the power supply during register initialization and afterwards enable the power supply b3 4 grays when combined with AUX 03 bits 1 and 2 application specific b2 8 bit LCD data width pan...

Page 111: ...pically the same as Total Display Line Count AUX 0Ah AUX 04h bits 1 0 of AUX 0Bh bits 1 0 of AUX 05h see Section 5 4 Split Screen on page 45 AUX 0Bh 0000 0000 bits 7 2 don t care recommend clearing bits bits 1 0 bits 9 8 of Screen 1 Display Line Count application specific see AUX 0Ah AUX 0Ch 0000 0000 normally programmed to 00h panel specific bits 7 0 use fixed default non display period AUX 0Dh 0...

Page 112: ...data AUX 0Fh 0000 0101 write Blue data AUX 0Eh 0000 0111 increment palette address AUX 0Fh 0000 1111 write Red data AUX 0Fh 0000 1111 write Green data AUX 0Fh 0000 0000 write Blue data AUX 0Eh 0000 1000 increment palette address AUX 0Fh 0000 1111 write Red data AUX 0Fh 0000 1111 write Green data AUX 0Fh 0000 0001 write Blue data AUX 0Eh 0000 1001 increment palette address AUX 0Fh 0000 1101 write R...

Page 113: ...n application specific b4 LCDE LCDENB pin set to enable specific power supply design for S5U13503B00C set bit to 1 to enable power supply application specific Write one pixel to the top left corner of the display s second panel If the S5U13503B00C evaluation board is used in indexed mode there are two video memory banks which begin at D000 0000 2 banks x 64K per bank see the note on page 14 If the...

Page 114: ... only available on monochrome panels and can only be displayed in black and white no Look Up Table is used 3 1 2 Memory Organization for Two Bit Pixels 4 Colors Gray Shades To store two bit pixels four pixels are grouped into one byte of display memory as shown below Figure 2 Pixel Storage For 2 Bits 4 Colors Gray Shades In One Byte Of Display Memory When these pixels are shown Pixel 0 is seen to ...

Page 115: ...s 256 Colors To store eight bit pixels one pixel is stored in one byte of display memory as shown below Figure 4 Pixel Storage For 8 Bits 256 Colors In One Byte Of Display Memory As shown above the 256 color pixel is divided into three parts three bits for red three bits for green and two bits for blue The red bits represent an index into the red LUT the green bits represent an index into the gree...

Page 116: ...position Green palette is arranged into four 4 position banks These two bits control which bank is currently selected These bits have no effect in 16 level gray color display modes 4 bits pixel In 256 color display modes 8 bit pixel the 16 position Green palette is arranged into two 8 position banks for the display of green colors Only bit 0 of these two bits controls which bank is currently selec...

Page 117: ...e display of red colors Only bit 0 of these two bits controls which bank is currently selected These bits have no effect in all gray shade or 16 color display modes bit 5 4 Blue Bank Bits 1 0 In both the 4 and 256 color display modes the 16 position Blue palette is arranged into four 4 position banks for the display of blue colors These two bits control which bank is currently selected These bits ...

Page 118: ... pixel size these LUTs will provide from 1 to 4 banks 2 bits per pixel 4 colors In this format the pixel is an index into the red green and blue LUTs Each color LUT supports 4 banks see Section 3 2 5 Four Colors Two Bits Pixel in Color Mode on page 28 4 bits per pixel 16 colors In this format the pixel is an index into the red green and blue LUTs Each color LUT supports only one bank see Section 3...

Page 119: ... Initialize the Look Up Table for 256 Colors Bank 0 Only Table 3 5 shows the color LUTs with intensities starting from black index 0 and finishing in maximum color intensity at the largest index available for the color in bank 0 For example the red LUT would have a maximum intensity at index 07h the green LUT would have a maximum intensity at index 07h and the blue LUT would have a maximum intensi...

Page 120: ...th gray shades starting from black index 0 and finishing in white index 15 or 0Fh 1 Write LUT index to Look Up Table Address Register AUX 0Eh 2 Write LUT entry value to Look Up Table Data Register AUX 0Fh 3 Repeat steps 1 and 2 until all 16 LUT entries have been written Table 3 6 S1D13503 Black To White Look Up Table Index hex Look Up Table hex Index hex Look Up Table hex 0 0 8 8 1 1 9 9 2 2 A A 3...

Page 121: ...a 3 Write LUT entry back Write LUT index to Look Up Table Address Register AUX 0Eh Write New LUT Entry to Look Up Table Data Register AUX 0Fh 4 Repeat steps 1 to 3 until all 16 LUT entries have been changed If Table 3 6 was previously programmed into the S1D13503 the new inverted LUT would be the following 3 2 3 Black and White One Bit Pixel When the S1D13503 is configured for one bit pixels the m...

Page 122: ...entries in the 16 entry LUT represent the first bank bank 0 The following four entries in the LUT rep resent the second bank bank 1 etc Consequently bank 2 starts at LUT index 8 as shown below Monochrome green Bank 2 is shown in Figure 5 2 Write LUT index to Look Up Table Address Register AUX 0Eh For bank 2 the index will one of the following values 08h 09h 0Ah or 0Bh 3 Write LUT entry value to Lo...

Page 123: ...reen Look Up Table 0 1 2 3 2 bit pixel data 0 1 2 3 0 1 2 3 0 1 2 3 Bank 0 Bank 1 Bank 2 Bank 3 Bank Select bits 1 0 Aux 0E bits 7 6 4 bit display data output Bank Select Logic Note the above depiction is intended to show the display data output path only The CPU R W access to the individual Look Up Tables is not affected by the various banking configurations Downloaded from Elcodis com electronic...

Page 124: ...UT index 0Ch as shown below Red Bank 3 is shown in Figure 6 2 Write LUT index and Red LUT selection to Look Up Table Address Register AUX 0Eh AUX 0Eh LUT index OR 0001 0000b For bank 3 the index will one of the following values 0Ch 0Dh 0Eh or 0Fh so the value written to AUX 0Eh will be one of the following 1Ch 1Dh 1Eh or 1Fh This selects the Red LUT only indexes C D E and F 3 Write LUT entry value...

Page 125: ...lect bits 1 0 Aux 0F bits 7 6 Bank Select Logic 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 Bank 0 Bank 1 Bank 2 Bank 3 Green Bank Select bits 1 0 Aux 0E bits 7 6 Bank Select Logic 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 Bank 0 Bank 1 Bank 2 Bank 3 Blue Bank Select bits 1 0 Aux 0F bits 5 4 Bank Select Logic RED Look Up Table GREEN Look Up Table Blue Look Up Table 4 bit GREEN 4 bit RED display data output display data...

Page 126: ...de When the S1D13503 has 4 bit monochrome pixels each pixel can index into one of 16 LUT entries The LUT bank bits are ignored in this mode 16 Level Gray Shade Mode Figure 7 16 Level Gray Shade Mode Look Up Table Architecture 4 bit pixel data P3 P2 P1 P0 4 bit Look Up Table data output msb lsb Green Look Up Table 16x4 0 1 2 3 C D E F Downloaded from Elcodis com electronic components distributor ...

Page 127: ...e 3 10 Simulation Of First 16 Entries Of Standard VGA Palette Address Red Green Blue Address Red Green Blue 00 00 00 00 08 00 00 00 01 00 00 0A 09 00 00 0F 02 00 0A 00 0A 00 0F 00 03 00 0A 0A 0B 00 0F 0F 04 0A 00 00 0C 0F 00 00 05 0A 00 0A 0D 0F 00 0F 06 0A 0A 00 0E 0F 0F 00 07 0A 0A 0A 0F 0F 0F 0F 4 bit pixel data Red Look Up Table 16x4 0 1 2 3 C D E F Green Look Up Table 16x4 0 1 2 3 C D E F Blu...

Page 128: ...le For 256 Color Mode on page 23 and only bank 0 were used for each of the three colors This method results in each color index inside the pixel to represent its respective color intensity see Table 3 11 below Table 3 11 Examples Of 256 Pixel Colors Using Linear LUT Pixel Value binary Color Pixel Value binary Color 000 000 00 black 000 000 00 black 000 000 10 dark blue 000 000 11 bright blue 000 1...

Page 129: ...1 2 3 4 5 6 7 Bank 1 Bank Select Logic 3 bit pixel data 0 1 2 3 2 bit pixel data 0 1 2 3 0 1 2 3 0 1 2 3 Bank 0 Bank 1 Bank 2 Bank 3 Blue Bank Select bits 1 0 Aux 0F bits 5 4 Bank Select Logic Blue Look Up Table Green Look Up Table Green Bank Select bit Aux 0E bit 6 Red Bank Select bit Aux 0F bit 6 7 6 5 4 3 2 1 0 R2 R1 R0 G2 G1 G0 B1 B0 256 Color Data Format 4 bit GREEN 4 bit RED display data out...

Page 130: ...it start address i e word access Note The absolute address into display memory is determined by the Memory Mapping Address which is set by the reset state of VD13 VD15 The Screen 1 Display Start Address is the memory address corresponding to the first displayed pixel top left corner In a dual panel configuration screen 1 refers to the upper half of the display While in a single panel configuration...

Page 131: ...be displayed at the same time on one display The Screen 2 Display Start Address is the memory address corresponding to the first pixel of the second image stored in display memory To display screen 2 refer to AUX 0A Screen 1 Display Line Count Register LSB on page 45 AUX 08 Screen 2 Display Start Address Register LSB I O address 1000b Read Write Screen 2 Display Start Addr Bit 7 Screen 2 Display S...

Page 132: ...d from the base port address 2 To access bank 1 write to base port address 2 The values read from or written to base port address 2 are not important The start of bank 0 repre sents the top left corner of display memory For the S5U13503B00C the Screen Display Start Address Registers are always in reference to the display memory address D000 0000h bank 0 Writing 0 to a Display Start Address Registe...

Page 133: ...play is at tached to the S5U13503B00C evaluation board Normally images are loaded at the start of display memory D000 0000h bank 0 so the display start address registers must be set to 0000h words AUX 06h 00h AUX 07h 00h Example 10 Program the Display Start Address Registers for a dual panel LCD Refer to Section 5 4 3 1 Displaying a Single Image on a Dual Panel on page 50 Example 11 Determine if t...

Page 134: ...ay Shades Table 4 1 Memory Size Requirements Display Resolution Pixel Storage Memory Requirements Bits Pixel Colors Gray Shades Bytes Hex 320 x 240 1 2 9 600 0000 2580 2 4 19 200 0000 4B00 4 16 38 400 0000 9600 8 256 76 800 0001 2C00 480 x 240 1 2 14 400 0000 3840 2 4 28 800 0000 7080 4 16 57 600 0000 E100 8 256 115 200 0001 C200 640 x 200 1 2 16 000 0000 3E80 2 4 32 000 0000 7D00 4 16 64 000 0000...

Page 135: ...s Figure 12 Memory Map Example For 640 x 200 LCD Panel With 16 Colors Gray Shades Offset hex Offset hex 0000 0000 Scan Line 0 0000 013F 0000 0140 Scan Line 1 027F 0001 2980 Scan Line 238 0001 2ABF 0001 2AC0 Scan Line 239 0001 2BFF Offset hex Offset hex 0000 Scan Line 0 013F 0140 Scan Line 1 027F F780 Scan Line 198 F8BF F8C0 Scan Line 199 F9FF Downloaded from Elcodis com electronic components distr...

Page 136: ... with 128K of display memory a 640x400 16 gray image can be stored If the output display size is 320x240 then the whole image can be seen by changing display starting addresses through AUX 06 and 07 and AUX 08 and 09 Note that a virtual screen can be produced on either a single or dual panel In 8 bit memory interface if the Address Pitch Adjustment is not equal to zero a virtual screen with a line...

Page 137: ...ce is 16 bits 1 Initialize the S1D13503 registers for a 320x240 panel 2 Determine whether the Address Pitch Adjustment Register refers to bytes or words Since the Memory Interface is set to 16 bits the Address Pitch Adjustment Register refers to words 3 Determine the number of pixels per unit referred to by the Address Pitch Adjustment Register The Address Pitch Adjustment Register refers to units...

Page 138: ...Bank 0 Only on page 23 3 Calculate the display memory map See Figure 11 Memory Map Example For 320 x 240 LCD Panel With 256 Colors on page 39 4 Write font to display memory In a general purpose program the entire bitmapped font would be placed in an array As characters are to be dis played the program would choose the appropriate bitmap select the proper position on the screen and write to dis pla...

Page 139: ...to the S5U13503B00C implementation and is used to select one of two 64K display memory banks a read from this port selects bank 0 and a write to this port selects bank 1 Note that the values read from or written to the Memory Banking port are not important Offset hex Offset hex 0000 F F F F F F F F F F F F 0 0 0 0 F F F F F F F F F F F F F F 0 0 F F F F 0 0 0 0 0 0 F F F F 0 0 F F F F F F F F F F ...

Page 140: ...ough 12 See Summary of Configuration Options in the S1D13503 Hardware Functional Specification Drawing Office No X18A A 001 xx To access the internal 16 registers of the S1D13503 simply perform I O read write functions to the absolute address as defined in the previous paragraph There is no memory banking available in direct addressing mode Example 15 Write 12h to register 08h on the S5U13503B00C ...

Page 141: ... as dictated by the screen 2 display start address registers AUX 08 and AUX 09 Two different images can be displayed when using a dual panel configuration by changing the screen 2 dis play start address However by using this method screen 2 is limited to the lower half of the display This register is ignored in dual panel mode Note See Section 4 2 2 Display Start Address Registers on page 37 for a...

Page 142: ...Calculate the number of bytes per scan line 3 Determine the display memory location for image 1 For simplicity assign the beginning of display memory as the starting address of image 1 see Figure 16 For the S5U13503B00C this address is D000 0000h bank 0 Figure 16 Memory Map For Split Screen 4 Program the Screen 1 Display Start Address Register to point to the beginning of image 1 Since image 1 is ...

Page 143: ...e shown minus 1 By changing the line count image 2 appears to move up or down the display If the line count is set to the maximum number of visible scan lines 1 only image 1 is shown AUX 0Ah LSB of visible scan lines 1 EFh AUX 0Bh MSB of visible scan lines 1 00h If the line count is set to 0 then the first scan line of image 1 is shown followed by the first part of image 2 It is not possible to sh...

Page 144: ...s refer to words the image must be aligned in memory such that the beginning is found on a word boundary the least significant bit of the memory address must be 0 2 Calculate the number of bytes per scan line 3 Determine the display memory location for image 1 For simplicity assign the beginning of display memory as the starting address of image 1 see Figure 16 For the S5U13503B00C this address is...

Page 145: ...UX 09h 4Bh 8 Write both image 1 and image 2 to their respective locations in display memory Notes When using a dual panel the Screen 1 Display Line Count Register is ignored by the S1D13503 Once the two Display Start Address Registers are programmed the top panel will show the beginning of image 1 and the bottom panel will show the beginning of image 2 see Figure 18 Figure 18 640 x 480 Dual Panel ...

Page 146: ...mage on a Dual Panel The following is the procedure to show a single image on a dual panel LCD In this procedure the single image is broken into two smaller images the first half of the image is placed on the top panel and the second half is placed on the bottom panel For this example the S5U13503B00C is used with a 4 gray shade 640 x 480 dual panel LCD the Memory Interface is set to 16 bits to su...

Page 147: ...half of the image Place the second half of the image immediately after the first half see Figure 19 Assign the starting address for the second half as follows Note that if the address of the second half of the image is larger than D000 FFFFh then switch to bank 1 reset the segment to D000h and keep the offset For example if the address of the second half of the image were D001 9200h bank 0 then th...

Page 148: ...emory To do so initialize the registers as described in Section 2 INITIALIZING THE S1D13503 on page 10 but with the following exception the Address Pitch Adjustment Register in the S1D13503 must be set to create a virtual display see Section 5 1 Virtual Displays on page 40 for more information 5 5 2 Panning Right and Left To pan to the right increase the value in the Screen 1 Display Start Address...

Page 149: ...ords in a virtual scan line to the Screen 1 Display Start Address Register In this example the Screen 1 Display Start Address points to the beginning of the image 3 Program the Screen 1 Display Start Address AUX 06h A0h AUX 07h 00h 4 This step is for dual panels only Add the number of words in a virtual scan line to the Screen 2 Display Start Address Register In this example the Screen 2 Display S...

Page 150: ...r reduction in the hand held devices market These modes can be enabled by setting the 2 Power Save bits AUX 03h bits 7 6 The various settings are 5 6 2 1 Power Save Mode 1 Power Save Mode 1 would typically be used when power savings are required and display memory accesses may occur The disadvantage is that since the oscillator is running this mode consumes more power that Power Save Mode 2 5 6 2 ...

Page 151: ...s This delay time is dependent upon the specific power sup ply design as well as the display s electrical characteristics For the S5U13503B00C this time is about 0 5 seconds 4 Enter power saving mode by writing the appropriate bits 7 6 of AUX 03h 5 6 2 5 Programming to Exit Power Down Mode When the LCDENB pin is used to control an external LCDBIAS power supply the following sequence is recommended...

Page 152: ... 4 Refer to Table 6 1 below to decode chip ID Note If the registers have already been initialized after power up the ID bits in AUX 0Eh cannot be used since these bits are also used for the RGB index It is recommended to always store the chip ID immedi ately after power up and before any register initialization Table 6 1 ID Bit Usage Chip Aux 0E bit 5 bit 4 Power On or RESET S1D13503 0 0 reserved ...

Page 153: ... n f n For example if there is a 320 x 240 color single panel LCD 8 bit interface format 2 with a port address of 310h type 13503DEMO t SINGLE x 320 y 240 d COLOR i 8 p 310 f 2 When 13503DEMO is started output will be sent to the standard output device This output will present a menu of numbered options Figure 20 Display For 13503DEMO EXE where t SINGLE DUAL x horizontal panel size in pixels from ...

Page 154: ...rgc char argv int ch CheckArguments argc argv printf Initializing n Initialize SetDisplay OFF ClearLCDScreen switch GetID PanelPortAddr case ID_13502 printf Detected S1D13502 n n Quit break case ID_13502 printf Detected S1D13502 n n Quit break case ID_13503 printf Detected S1D13503 n break default printf ERROR Could not detect chip n n Quit break ShowMenu while ch getch ESC switch ch case 1 ShowRe...

Page 155: ...ter Programming Notes and Examples S1D13503 Issue Date 01 01 30 X18A G 002 06 break case 2 GrayShadeBars break case 3 SplitScreen break case 4 PanScroll break case 5 PowerSaving break case ESC exit 0 Downloaded from Elcodis com electronic components distributor ...

Page 156: ...ytesPerScanLine void Initialize void static unsigned int val val2 static unsigned int x if PanelD PANEL_MONO PanelGrayLevel 16 else PanelGrayLevel 256 Mode Register Display OFF Panel SINGLE Mask XSCL NOT MASKED LCDE NOT ENABLED Gray Shade Color 16 Gray Shades bit is ignored for 256 colors LCD Data Width 8 bit data transfer Memory Interface 16 bits RAMS Addressing for 8Kx8 SRAM val 0x0C if Interfac...

Page 157: ...x Horizontal Resolution 1 Memory Interface Width switch PanelGrayLevel case 2 val PanelX 16 1 For black and white mode break case 4 val PanelX 8 1 For 4 gray shades colors break case 16 val PanelX 4 1 For 16 gray shades colors break case 256 val PanelX 2 1 For 256 colors break WriteRegister 2 val 0xff Line Byte Word Count Register val2 val 8 0x01 if PanelD PANEL_COLOR val2 0x06 Select color mode a...

Page 158: ...ed that all panels smaller than 400 lines use a 4 bit interface However newer panels which are less than 400 lines may use an 8 bit interface Consequently this program must be told which interface to use Set the Mask XSCL bit to MASKED 1 when using a 4 bit interface if Interface 4 val ReadRegister 1 val 0xfb Set LCD Data Width to 4 bit data transfer val 0x20 Set Mask XSCL to MASKED WriteRegister 1...

Page 159: ...egister 7 0 Screen 2 Display Start Address Register If using a dual panel the Screen 2 Display Start Address must point to the second half of the image in video memory if PanelType TYPE_DUAL val unsigned int ReadRegister 3 0x01 8 ReadRegister 2 val val PanelY 2 WriteRegister 8 val 0xff WriteRegister 9 val 8 else On a single panel Screen 1 was programmed to show all of its lines Consequently Screen...

Page 160: ...gister 0x0e x WriteRegister 0x0f MonoLUT16 x else for x 0 x 16 x WriteRegister 0x0e x Auto increment mode selected WriteRegister 0x0f ColorLUT256Red x WriteRegister 0x0f ColorLUT256Green x WriteRegister 0x0f ColorLUT256Blue x Now that system is initialized set DISPLAY ON and enable LCDE val ReadRegister 1 val 0x90 DISPLAY ON LCDE enabled WriteRegister 1 val GetID This function returns the Chip ID ...

Page 161: ...TED If the chip was just powered up and no registers have been initialized then use the following code outp PortAddr 0x0e switch inp PortAddr 1 0x30 case 0x00 ChipID ID_13503 break case 0x20 ChipID ID_13502 break case 0x30 ChipID ID_13502 break default ChipID ID_NOT_DETECTED break return ChipID Downloaded from Elcodis com electronic components distributor ...

Page 162: ...c unsigned char x static unsigned char red green blue printf S1D13503 Registers for x 0 x 16 x printf 02X ReadRegister x printf nS1D13503 Lookup Table for x 0 x 16 x WriteRegister 0x0e x red ReadRegister 0x0f green ReadRegister 0x0f blue ReadRegister 0x0f if x 7 0 printf n printf 02X 02X 02X red green blue ShowMenu FUNCTION GrayShadeBars DESCRIPTION Displays a series of vertical bars each with a d...

Page 163: ...r Color4 Vertical Bars at 4 Colors static char Gray16 Vertical Bars at 16 Gray Shades static char Color16 Vertical Bars at 16 Colors static char str printf Displaying Vertical Bars n Initialize SetDisplay OFF ClearLCDScreen Access memory banks FP_SEG pVideo 0xd000 FP_OFF pVideo 0x0000 if PanelD PANEL_MONO Select black and white mode val ReadRegister 3 val 0x04 Set AUX 03 bit 2 val 0xfd Clear AUX 0...

Page 164: ...0xfe Clear bit 0 val2 val 8 0x01 WriteRegister 3 val2 Mode Register 1 PanelGrayLevel 2 ShowVerticalBars pVideo 0 Show text The lightest gray shade is set to PanelGrayLevel 1 ShowText pVideo BANK0 Vertical Bars for Black and White PanelGrayLevel 1 SetDisplay ON Delay 2000 SetDisplay OFF ClearLCDScreen Select 4 gray shades colors if PanelD PANEL_MONO val ReadRegister 1 val 0xf7 Clear AUX 01 bit 3 Wr...

Page 165: ...riteRegister 0x0f ColorLUT4Blue x str Color4 Update Line Byte Word Count register for 4 colors gray shades Since 4 colors gray shades corresponds to 4 pixels per byte there are x horizontal pixels 4 bytes per scan line This means that there are x horizontal pixels 8 words per scan line Since the Memory Interface is set to 16 bits the Line Byte Word Count refers to words val PanelX 8 1 BytesPerScan...

Page 166: ...K 1 PanelGrayLevel 1 Delay 2000 val 0x3f val 0x80 WriteRegister 0x0e val ShowVerticalBars pVideo 0 ShowText pVideo BANK0 str PanelGrayLevel 1 ShowText pVideo BytesPerScanLine 8 BANK0 BANK 2 PanelGrayLevel 1 Delay 2000 val 0xc0 WriteRegister 0x0e val ShowVerticalBars pVideo 0 ShowText pVideo BANK0 str PanelGrayLevel 1 ShowText pVideo BytesPerScanLine 8 BANK0 BANK 3 PanelGrayLevel 1 Delay 2000 SetDi...

Page 167: ...0f ColorLUT16Red x WriteRegister 0x0f ColorLUT16Green x WriteRegister 0x0f ColorLUT16Blue x str Color16 Update Line Byte Count register for 16 colors gray shades Since 16 colors gray shades corresponds to 2 pixels per byte there are x horizontal pixels 2 bytes per scan line This means that there are x horizontal pixels 4 words per scan line Since the Memory Interface is set to 16 bits the Line Byt...

Page 168: ...Register 3 val Update Lookup Table for 256 colors for x 0 x 16 x WriteRegister 0x0e x WriteRegister 0x0f ColorLUT256Red x WriteRegister 0x0f ColorLUT256Green x WriteRegister 0x0f ColorLUT256Blue x Update Line Byte Word Count register for 256 colors Since 256 colors have one pixel per byte there are x horizontal pixels bytes per scan line This means that there are x horizontal pixels 2 words per sc...

Page 169: ... to the LCD panel Text must only contain the letters A Z and the space character All other characters are replaced by spaces NOTES It is assumed that a pixel set to a value of 0 represents the background color black void ShowText unsigned char _far pVideoStart unsigned char bank char str int color static const unsigned char pFont static unsigned char _far pVideoFirstColumn static unsigned char _fa...

Page 170: ...x78 0xCC 0xCC 0x78 0x00 8 0x78 0xCC 0xCC 0x7C 0x0C 0x18 0x70 0x00 9 0x00 0x30 0x30 0x00 0x00 0x30 0x30 0x00 0x00 0x30 0x30 0x00 0x00 0x30 0x30 0x60 0x18 0x30 0x60 0xC0 0x60 0x30 0x18 0x00 0x00 0x00 0xFC 0x00 0x00 0xFC 0x00 0x00 0x60 0x30 0x18 0x0C 0x18 0x30 0x60 0x00 0x78 0xCC 0x0C 0x18 0x30 0x00 0x30 0x00 0x7C 0xC6 0xDE 0xDE 0xDE 0xC0 0x78 0x00 0x30 0x78 0xCC 0xCC 0xFC 0xCC 0xCC 0x00 A 0xFC 0x66 ...

Page 171: ...x00 i 0x0C 0x00 0x0C 0x0C 0x0C 0xCC 0xCC 0x78 j 0xE0 0x60 0x66 0x6C 0x78 0x6C 0xE6 0x00 k 0x70 0x30 0x30 0x30 0x30 0x30 0x78 0x00 l 0x00 0x00 0xCC 0xFE 0xFE 0xD6 0xC6 0x00 m 0x00 0x00 0xF8 0xCC 0xCC 0xCC 0xCC 0x00 n 0x00 0x00 0x78 0xCC 0xCC 0xCC 0x78 0x00 o 0x00 0x00 0xDC 0x66 0x66 0x7C 0x60 0xF0 p 0x00 0x00 0x76 0xCC 0xCC 0x7C 0x0C 0x1E q 0x00 0x00 0xDC 0x76 0x66 0x60 0xF0 0x00 r 0x00 0x00 0x7C 0...

Page 172: ... ch str if ch ch MAX_FONT 1 ch pFont font ch 0 for y 0 y 8 y pVideo pVideoFirstColumn Video 0 val pFont Since there are 2 gray shades each bit in the font will be represented in video memory as a one bit pixel if val 0x80 Video color 7 if val 0x40 Video color 6 if val 0x20 Video color 5 if val 0x10 Video color 4 if val 0x08 Video color 3 if val 0x04 Video color 2 if val 0x02 Video color 1 if val 0...

Page 173: ...4 If there are 4 colors gray levels there are 4 pixels byte color 0x03 while str 0 ch str if ch ch MAX_FONT 1 ch pFont font ch 0 for y 0 y 8 y pVideo pVideoFirstColumn Video 0 val pFont Since there are 4 colors gray shades each bit in the font will be represented in video memory as a two bit pixel if val 0x80 Video color 6 if val 0x40 Video color 4 if val 0x20 Video color 2 if val 0x10 Video color...

Page 174: ...k pVideo bank pVideoFirstColumn BytesPerScanLine pVideoStart 2 Point to next character pVideoFirstColumn pVideoStart break case 16 color 0x0f while str 0 ch str if ch ch MAX_FONT 1 ch pFont font ch 0 for y 0 y 8 y pVideo pVideoFirstColumn Video 0 val pFont Since there are 16 colors gray shades each bit in the font will be represented in video memory as a four bit pixel if val 0x80 Video color 4 if...

Page 175: ...nk pVideo bank Video 0 if val 0x08 Video color 4 if val 0x04 Video color pVideo unsigned char Video CheckBank pVideo bank Video 0 if val 0x02 Video color 4 if val 0x01 Video color pVideo unsigned char Video CheckBank pVideo bank pVideoFirstColumn BytesPerScanLine pVideoStart 4 Point to next character pVideoFirstColumn pVideoStart break case 256 while str 0 ch str if ch ch MAX_FONT 1 ch pFont font ...

Page 176: ...eo CheckBank pVideo bank val 1 pVideoFirstColumn BytesPerScanLine pVideoStart 8 Point to next character pVideoFirstColumn pVideoStart break FUNCTION SplitScreen DESCRIPTION Show split screen INPUTS None RETURN VALUE None void SplitScreen void static unsigned char _far pVideoImage1 static unsigned char _far pVideoImage2 static unsigned long ImageSize static unsigned int OriginalLineCount static uns...

Page 177: ...nelX 4 break case 16 BytesPerScanLine PanelX 2 break case 256 BytesPerScanLine PanelX break ShowVerticalBars pVideoImage1 0 Calculate starting video memory location for image 2 by finding the last location of image 1 ImageSize unsigned long BytesPerScanLine PanelY Because the image size is limited to a maximum of 320 x 240 and there is 128k of video memory there is enough memory available FP_SEG p...

Page 178: ... is because the Memory Interface is set to 16 bits val unsigned int ImageSize 2 WriteRegister 8 unsigned int val 0xff WriteRegister 9 unsigned int val 8 SetDisplay ON If this is a dual panel then the split screen has just been shown Otherwise set up the Screen 1 Display Line Count register for single panels if PanelType TYPE_SINGLE OriginalLineCount unsigned int ReadRegister 0x0b 0x03 8 ReadRegist...

Page 179: ...f Total Display Line Count WriteRegister 0x0b val 8 0x03 Total Disp Line Cnt WF Count Delay DELAY_SHORT val MinLineCount WriteRegister 0x0a val 0xff Total Display Line Count Reg WriteRegister 0x0b val 8 0x03 Total Disp Line Cnt WF Count Delay 500 ShowMenu void SetStartAddress int x int y int addr switch PanelGrayLevel case 16 addr unsigned int x 2 VIRTUAL_X 2 y 2 break case 256 addr unsigned int x...

Page 180: ... BytesPerScanLine 2 BytesPerScanLine VIRTUAL_X 2 break case 256 pitch unsigned int VIRTUAL_X BytesPerScanLine 2 BytesPerScanLine VIRTUAL_X break WriteRegister 0x0d pitch Access memory banks FP_SEG pVideo 0xd000 FP_OFF pVideo 0x0000 Display random blocks of data To do so a text character will be used This character sets all pixels in a character region so a block is shown at the specified gray shad...

Page 181: ...ter in the font table is a solid block character ShowText pVideo bank x80 color ShowBorders Move virtual display from 0 0 to MaxX 0 MaxX unsigned int VIRTUAL_X PanelX MaxY unsigned int VIRTUAL_Y PanelY SetDisplay ON for x 0 x MaxX x SetStartAddress x 0 Delay DELAY_SHORT for y 0 y MaxY y SetStartAddress MaxX y Delay DELAY_SHORT for x MaxX x 0 x SetStartAddress x MaxY Delay DELAY_SHORT for y MaxY y ...

Page 182: ...are the steps to enter a power save mode Step 1 Turn off display val ReadRegister 1 val 0x7f WriteRegister 1 val Step 2 Disable LCDE turn off LCD power supply For the S5U13503B00C set LCDE bit to 0 val ReadRegister 1 val 0xef WriteRegister 1 val Step 2 Wait for LCD power supply to drop to zero volts For the S5U13503B00C wait about a half second Delay 500 Step 3 Enter Power Save Mode val ReadRegist...

Page 183: ...he steps to exit a power save mode Step 1 Exit Power Save Mode val ReadRegister 3 val 0x3f WriteRegister 3 val Cancel power saving mode 2 Step 2 Enable LCDE turn on LCD power supply For the S5U13503B00C set LCDE bit to 1 val ReadRegister 1 val 0x10 WriteRegister 1 val Step 3 Turn on display val ReadRegister 1 val 0x80 WriteRegister 1 val ShowMenu Downloaded from Elcodis com electronic components d...

Page 184: ...el as an index into an array of colors or gray shades panel The circuitry and viewable area of an LCD display which supports a single image LCD displays may have one or two panels panning The right or left movement of the viewport in a virtual display pixel Picture Element A pixel is seen as a dot on the display and can be shown using one of several different colors or gray shades Combining pixels...

Page 185: ...I O address 1000b RW Screen 2 Display Start Address low byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AUX 09 SCREEN 2 DISPLAY START ADDRESS REGISTER MSB I O address 1001b RW Screen 2 Display Start Address high byte Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 AUX 0A SCREEN 1 DISPLAY LINE COUNT REGISTER LSB I O address 1010b RW Screen 1 Display Line Count low byte Bit 7 Bit 6 Bit 5 ...

Page 186: ...S1D13503F00A Register Summary X18A Q 002 05 Page 2 01 03 02 Downloaded from Elcodis com electronic components distributor ...

Page 187: ... in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other tradema...

Page 188: ...pson Research and Development Vancouver Design Center S1D13503 13503SHOW EXE Display Utility X18A B 001 05 Issue Date 01 01 29 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 189: ...e file1 gif is the first screen image to be displayed file2 gif is the second screen image to be displayed i inverts all displayed images show as negative used for some monochrome panels works in monochrome mode only k exit the program and keep the image on the display useful in batch file execution such as demonstrations v verbose mode useful to determine GIF information if it is not known d leav...

Page 190: ...d number of colors gray shades If there is insufficient memory for screen two 13503SHOW will not accept the two image files and will generate an error message When loading two GIF images it may take several seconds of apparent inactivity to load the second image into memory The GIF format must be 2 16 or 256 color non interlaced GIF89a format 13503SHOW will clear the screen when the Esc key is pre...

Page 191: ... evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks...

Page 192: ...pson Research and Development Vancouver Design Center S1D13503 13503VIRT EXE Display Utility X18A B 002 05 Issue Date 01 01 29 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 193: ...e image on the display useful in batch file execution for demonstrations produces a usage message The program draws a test pattern of two images on the display The user can navigate throughout either image using the numeric keypad Use the arrow keys to pan and scroll the screen Home to go to the top left PG UP to go to the top right End to go to the bottom left Pg Dn to go to the bottom right and ...

Page 194: ...Date 01 01 29 Comments 13503VIRT requires 13503BIOS COM to be loaded prior to running Program Messages ERROR This program requires 13503BIOS to be loaded The program 13503BIOS COM must be run before 13503VIRT EXE Load 13503BIOS COM and then re run 13503VIRT EXE Downloaded from Elcodis com electronic components distributor ...

Page 195: ...evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks ...

Page 196: ... 2 Epson Research and Development Vancouver Design Center S1D13503 13503BIOS COM Utility X18A B 003 05 Issue Date 01 01 29 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 197: ...ctory that is in the DOS path on your hard drive Usage 13503BIOS COM is run from the DOS command line The file 13503bios ini is the initialization file for 13503bios com and must reside in the same directory as 13503bios com This file contains the default run parameters for 13503bios com These parameters may be changed within the initialization file or for one time usage on the command line as fol...

Page 198: ... 64K bytes the S1D13503 video memory will reside at D000h to DFFFh For 128K bytes of S1D13503 video memory the memory will reside at C000h to DFFFh Program Messages ERROR panels greater than 640 pixels not supported More than 640 horizontal pixels has been specified for the panel in the command line ERROR panels greater than 480 lines not supported More than 480 vertical lines has been specified f...

Page 199: ... in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other tradema...

Page 200: ...pson Research and Development Vancouver Design Center S1D13503 13503MODE EXE Display Utility X18A B 004 05 Issue Date 01 01 29 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 201: ... the display useful for batch file execution for demonstrations 13503MODE displays a default color gray shade pattern as a series of vertical or horizontal bars The pattern number of colors gray shades and current palette may be modified by the user when possible Instructions to modify these options appear when available An image other than the default one may be used as follows 1 run 13503bios co...

Page 202: ...e Date 01 01 29 Comments 13503MODE requires 13503BIOS COM to be loaded prior to running Program Messages ERROR This program requires 13503BIOS to be loaded The program 13503BIOS COM must be run before 13503MODE Load 13503BIOS COM and then re run 13503MODE EXE Downloaded from Elcodis com electronic components distributor ...

Page 203: ...e in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other tradem...

Page 204: ...pson Research and Development Vancouver Design Center S1D13503 13503PD EXE Power Down Utility X18A B 005 05 Issue Date 01 01 29 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 205: ...3PD is run from the DOS command line as follows 13503pd ModeNumber Where ModeNumber is a decimal number 0 1 or 2 for the desired power down mode Example typing the following command line activates power down mode 2 13503pd 2 ENTER Output from the program can be redirected to an external DOS device such as a terminal attached to the serial port such as COM1 as shown below 13503pd 2 com1 ENTER Strik...

Page 206: ...ill be disabled and all LCD signals are forced low Program Messages Power Down Mode xx is set The power down mode xx has been set This message may not be visible if the active display controller is the S1D13503 ERROR Cannot set power mode xx 13503PD EXE cannot set the power down mode requested either 13503BIOS COM is not loaded or the power down mode number exceeds 2 ERROR This program requires 13...

Page 207: ...se in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trade...

Page 208: ...son Research and Development Vancouver Design Center S1D13503 13503READ EXE Diagnostic Utility X18A B 006 05 Issue Date 01 01 29 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 209: ... Installation Copy the file 13503read exe to a directory that is in the DOS path on your hard drive Usage From DOS prompt type the following 13503read p n Where 13503read without any argument will read the S1D13503 registers including the palettes p is the S1D13503 port address in hex e g 310 produces a usage message Example to generate a report simply type 13503read port report txt and the inform...

Page 210: ... to ensure it is correct and re run the program ERROR 13503READ requires a port address 13503READ has not detected 13503BIOS COM to obtain the port address and no port address was specified on the command line Either specify a port address on the 13503READ command line or run 13503BIOS COM prior to running 13503READ ERROR 13503BIOS reports a port address of port which is different from the specifi...

Page 211: ...ur own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All oth...

Page 212: ...rch and Development Vancouver Design Center S1D13503 S5U13503B00C Rev 1 0 Evaluation Board User Manual X18A G 007 05 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 213: ...SA Bus Support 13 3 2 Non ISA Bus Support 14 3 3 SRAM Support 14 3 4 Monochrome LCD Support 14 3 5 Color LCD Support 15 3 6 Power Save Modes 15 3 7 Adjustable LCD Panel Negative Power Supply 15 3 8 Adjustable LCD Panel Positive Power Supply 15 3 9 Crystal Support 16 3 10 Oscillator Support 16 3 11 CPU Bus Interface Header Strips 16 3 12 Schematic Notes 16 Appendix A Parts List 17 Appendix B S5U135...

Page 214: ...rch and Development Vancouver Design Center S1D13503 S5U13503B00C Rev 1 0 Evaluation Board User Manual X18A G 007 05 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 215: ...Connector H1 Pinout 11 Table 2 6 CPU BUS Connector H2 Pinout 12 LIST OF FIGURES Figure 1 S5U13503B00C Rev 1 0 Schematic Diagram 1 of 7 18 Figure 2 S5U13503B00C Rev 1 0 Schematic Diagram 2 of 7 19 Figure 3 S5U13503B00C Rev 1 0 Schematic Diagram 3 of 7 20 Figure 4 S5U13503B00C Rev 1 0 Schematic Diagram 4 of 7 21 Figure 5 S5U13503B00C Rev 1 0 Schematic Diagram 5 of 7 22 Figure 6 S5U13503B00C Rev 1 0 ...

Page 216: ...rch and Development Vancouver Design Center S1D13503 S5U13503B00C Rev 1 0 Evaluation Board User Manual X18A G 007 05 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 217: ...e board space 1 1 Features 100 pin QFP5 package SMD technology for all appropriate devices 4 8 bit Monochrome STN LCD display support 4 8 16 bit Color STN LCD display support 8 16 bit ISA Bus support 5V operation Two terminal crystal support up to 25 0MHz Oscillator support 16 bit wide 128K bytes SRAM support Configuration Options Support for Software Power Save Modes On board adjustable LCD BIAS ...

Page 218: ...is board is pre set to use indexed I O with address 03y0 0000 0011 0yyy 000x where x is don t care and yyy can be configured with dip switch SW1 5 through SW1 7 The factory setting of yyy 001 i e I O address 0310 and 0311 Direct mapping I O is only available for Non ISA Bus support When using direct mapped I O the I O address is 03yx 0000 0011 0yyy xxxx where x is don t care and yyy can be configu...

Page 219: ...age 14 the following signal lines may require the 10K ohm pull up resistors installed VD4 R18 VD5 R19 VD6 R20 VD10 R21 and or VD13 R17 See the S1D13503 Hardware Functional Specification X18A A 001 xx page 21 for configuration details Table 2 3 Decoding Jumper Setting Description 1 2 2 3 JP1 Set to the same polarity as SW1 1 VD0 1 0 JP2 Set to the same polarity as SW1 5 VD7 1 0 JP3 Set to the same ...

Page 220: ... LD1 LD2 5 LD2 LD2 LD2 LD2 LD2 LD3 7 LD3 LD3 LD3 LD3 LD3 UD0 9 UD0 UD0 UD0 UD0 UD0 UD0 UD0 UD1 11 UD1 UD1 UD1 UD1 UD1 UD1 UD1 UD2 13 UD2 UD2 UD2 UD2 UD2 UD2 UD2 UD3 15 UD3 UD3 UD3 UD3 UD3 UD3 UD3 17 LD4b b From external logic see Section 3 5 for details 19 LD5b 21 LD6b 23 LD7b 25 UD4b 27 UD5b 29 UD6b 31 UD7b XSCL 33 XSCL XSCL XSCL XSCL XSCL XSCL XSCL WF XSCL2 35 XSCL2 LP 37 LP LP LP LP LP LP LP YD...

Page 221: ...03 11 GND Ground 12 GND Ground 13 SD8 Connected to DB8 of the S1D13503 14 SD9 Connected to DB9 of the S1D13503 15 SD10 Connected to DB10 of the S1D13503 16 SD11 Connected to DB11 of the S1D13503 17 GND Ground 18 GND Ground 19 SD12 Connected to DB12 of the S1D13503 20 SD13 Connected to DB13 of the S1D13503 21 SD14 Connected to DB14 of the S1D13503 22 SD15 Connected to DB15 of the S1D13503 23 RESET ...

Page 222: ... 12 SA9 Connected to AB9 of the S1D13503 13 SA10 Connected to AB10 of the S1D13503 14 SA11 Connected to AB11 of the S1D13503 15 SA12 Connected to AB12 of the S1D13503 16 SA13 Connected to AB13 of the S1D13503 17 GND Ground 18 GND Ground 19 SA14 Connected to AB14 of the S1D13503 20 SA15 Connected to AB14 of the S1D13503 21 SA16 Connected to U2 pin 20 22 SA17 Connected to AB17 of the S1D13503 23 SA1...

Page 223: ...with an 8 bit BIOS EPROM normally just one ROM on the adapter card the S5U13503B00C must be configured as follows SW1 1 open 8 bit operation necessary to prevent MEMCS16 conflict when reading VGA BIOS SW1 2 to 4 open for ISA bus support with indexed I O SW1 5 to 7 set as desired JP1 2 3 shorted to reflect SW1 1 polarity JP2 to JP4 to reflect SW1 5 to 7 polarity JP5 set as required for panel When t...

Page 224: ...nd H2 pin 21 must be physically connected to U2 pin20 in order to provide SA16 to U1 4 If it becomes necessary desirable to change the configuration information associated with VD 15 0 additional 10K Ohm pull up resistors can be added to those affected VD lines as there are place holders available on the PCB 3 3 SRAM Support The S5U13503B00C board supports 16 bit wide 128K byte SRAM In order for t...

Page 225: ... an output voltage from 14 V to 23 V and enabled disabled by the control signal LCDENB Note LCDENB is directly controlled by register AUX 01 bit 4 of the S1D13503 The VLCD power supply used on the S5U13503B00C requires a logic 1 to disable it As the signal LCDENB is a logic 0 at power up it is inverted by external logic to disable VLCD and prevent damaging the panel connected to the S5U13503B00C D...

Page 226: ...ator package is used capacitors C7 C8 and resistor R16 must be removed 3 11 CPU Bus Interface Header Strips All of the CPU Bus interface pins of S1D13503 with the exception of SA16 are connected to the header strips H1 and H2 for easy interface to a CPU Bus other than the ISA bus Refer to Table 2 5 CPU BUS Connector H1 Pinout on page 11 and Table 2 6 CPU BUS Connector H2 Pinout on page 12 for spec...

Page 227: ...Signal Transistor TO 92 PTH 13 3 R2 R13 R14 1K 1K Ohm 1206 5 14 2 R12 R15 100K 100K Ohm 1206 5 15 4 R3 R6 10K 10K Ohm 1206 5 16 1 R7 470K 470K Ohm 1206 5 17 1 R8 200K 200K Ohm Trim POT Spectrol 63S204T607 18 1 R9 10K 10K 10 pin SIP Part No 4610X 101 103 19 1 R10 14K 14K Ohm 1206 5 20 1 R11 100K 100K Ohm Trim POT Spectrol 63S104T607 21 1 R16 2M 2M Ohm 1206 5 22 1 R1 0 Ohm 0 Ohm 1206 1 23 5 R17 R21 ...

Page 228: ...4 98 DB5 99 DB6 100 DB7 1 DB8 4 DB9 5 DB10 6 DB11 7 DB12 8 DB13 9 DB14 10 DB15 11 LD0 77 LD1 76 LD2 75 LD3 74 UD0 73 UD1 72 UD2 71 UD3 70 WF XSCL2 80 LP 79 YD 78 XSCL 81 VA1 34 VA2 35 VA3 36 VA4 37 VA5 38 VA6 39 VA7 40 VA8 41 VA9 42 VA12 63 VA13 64 VA14 65 VA15 66 VD0 44 VD1 45 VD2 46 VD3 47 VD4 48 VD5 49 VD6 50 VD7 51 VD8 54 VD9 55 VD10 56 VD11 57 VD12 58 VD13 59 VD14 60 VD15 61 VWE 67 VOE 83 VCS...

Page 229: ... SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA1 IODC2TO10 SA 1 19 1 2 3 JP4 HEADER 3 1 2 3 JP3 HEADER 3 5V 5V SA5 SA6 SA7 SA8 SA9 ADDBIT4 ADDBIT5 ADDBIT6 5V P0 2 P1 4 P2 6 P3 8 P4 11 P5 13 P6 15 P7 17 Q0 3 Q1 5 Q2 7 Q3 9 Q4 12 Q5 14 Q6 16 Q7 18 G 1 P Q 19 VCC 20 GND 10 U3 74LS688 DW020 1 2 3 U5A 74LS09 D014 5V R2 1K MEMCS16 LCDPWR IOCS16 4 5 6 U5B 74LS09 D014 9 10 8 U5C 74LS09 D014 12 13 11 U5D 74LS0...

Page 230: ...OBIT4 NO BYTESWAP ISA INDEXING 8BITBI VD13 VD10 VD6 VD5 VD4 A0 20 A1 19 A2 18 A3 17 A4 16 A5 15 A6 14 A7 13 A8 3 A9 2 A10 31 A11 1 A12 12 A13 4 A14 11 OE 32 DO1 21 DO2 22 DO3 23 DO4 25 DO5 26 DO6 27 DO7 28 DO8 29 A15 7 WE 5 CS1 30 CS2 6 VDD 8 VSS 24 A16 10 NC 9 U7 SRM20100LTM 70 5V 5V VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 VA0 VA1 VA2 VA3 VA4 VA5 VA6 VA7 VA8 VA9 VA10 VA11 VA12 VA13 VA14 VA15 VA0 VA...

Page 231: ...D3 UD0 UD1 UD2 UD3 XSCL LP YD D0 3 D1 4 D2 7 D3 8 D4 13 D5 14 D6 17 D7 18 OC 1 CLK 11 Q0 2 Q1 5 Q2 6 Q3 9 Q4 12 Q5 15 Q6 16 Q7 19 VCC 20 GND 10 U11 74LS374 DW020 XSCL2 1 2 3 JP5 HEADER 3 12V LCDPWR VDDH LCDPWR LD4 LD5 LD6 LD7 UD4 UD5 UD6 UD7 5V WF XSCL2 WF XSCL2 SA1 SA3 SA5 SA7 SA9 SA11 SA13 SA15 SA17 SA19 IOR SMEMR 5V GND GND GND SA0 SA2 SA4 SA6 SA8 SA10 SA12 SA14 SA16 SA18 IOW SMEMW 5V GND GND G...

Page 232: ...0 9 IOCHRDY 10 AEN 11 SA19 12 SA18 13 SA17 14 SA16 15 SA15 16 SA14 17 SA13 18 SA12 19 SA11 20 SA10 21 SA9 22 SA8 23 SA7 24 SA6 25 SA5 26 SA4 27 SA3 28 SA2 29 SA1 30 SA0 31 AT1 AT CON A SD7 SD6 SD5 SD4 SD3 IOCHRDY IOEN SD2 SD1 SD0 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 12V SMEMW SMEMR IOW IOR REFRESH MEMCS16 IOCS16 5V MEMCS16 1 IOCS16 2 IRQ10 3 IRQ...

Page 233: ...1 D C _ I N 2 R E M O T E 3 G N D 4 G N D 5 G N D 6 G N D 7 G N D 8 N C9 G N D 1 0 G N D 1 1 D C _ O U T 1 2 U8 RD 0412 R7 470K C1 56uF 35V PSVCC 1 3 2 R8 200k R10 14k 5V C2 10uF 63V C3 10uF 63V C4 10uF 63V LOW ESR LOW ESR R13 1K PSGND 2 1 3 Q1 2N3906 2 1 3 Q2 2N3903 VLCD adjustable 14v to 23v R12 100K R14 1K R15 100K C5 56uF 35V D C _ O U T 1 D C _ O U T 2 N C3 G N D 4 G N D 5 V O U T _ A D J 6 N...

Page 234: ... S5U13503B00C SMD ISA BUS EVALUATION BOARD S MOS SYSTEMS INC 5V When the oscillator package is used the stabilizing capacitors and resistor must be removed NC 1 OUT 8 GND 7 VCC 14 U10 OSC 14 OSC1 OSC2 1 4 Y1 25 175Mhz R16 2M 5V C11 01uF C12 01uF BYPASS CAPACITORS 1 POWER PIN C7 7pF C8 7pF C13 01uF C14 01uF C15 01uF C16 01uF C17 01uF C18 01uF C19 01uF C22 01uF C20 01uF C21 01uF C23 01uF 12V 5V 12V ...

Page 235: ...aluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks ar...

Page 236: ...ge 2 Epson Research and Development Vancouver Design Center S1D13503 Power Consumption X18A G 006 04 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 237: ...ack and White 4 Grays 19 7 mW 24 3 mW 2 7 mW 2 7 mW less than 300 uW less than 300 uW 4 Input Clock 25 MHz LCD Panel Connected 640x480 Color VDD 3 0V 4 Colors 33 1 mW 2 7 mW less than 300 uW Table 1 2 S1D13503 Total Power Consumption 5 0V Operation Test Condition Gray Shades Colors Total Power Consumption Active Power Save Mode 1 2 1 Input Clock 6 MHz LCD Panel Connected 320x240 Monochrome VDD 5 0...

Page 238: ... 1 16 grays Condition 2 4 color Condition 2 16 color Condition 2 256 color Condition 3 BW Condition 3 4 color Condition 4 4 color S1D13503 Total Power Consumption 5V 0 20 40 60 80 100 120 140 ACTIVE PSM 1 PSM 2 Operating Mode Power mW Condition 1 BW Condition 1 4 grays Condition 1 16 grays Condition 2 4 color Condition 2 16 color Condition 2 256 color Condition 3 BW Condition 3 4 color Condition 4...

Page 239: ...se in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trade...

Page 240: ...son Research and Development Vancouver Design Center S1D13503 ISA Bus Interface Considerations X18A G 003 05 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 241: ...E 6 2 1 PAL Equations 7 2 2 Additional Discrete Logic Description 7 2 3 S1D13503 Default Setup 7 2 3 1 Configuration Options 7 2 3 2 Register Setting 8 3 8 BIT ISA BUS INTERFACE 9 3 1 S1D13503 Default Setup 10 3 1 1 Configuration Options 10 3 1 2 Register Setting 10 List of Figures Figure 1 16 Bit ISA Bus Implementation 6 Figure 2 8 Bit ISA Bus Implementation 9 Downloaded from Elcodis com electron...

Page 242: ...son Research and Development Vancouver Design Center S1D13503 ISA Bus Interface Considerations X18A G 003 05 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 243: ...d through the use of minimal external circuitry This application note describes the interface between the S1D13503 and the ISA Bus both 8 and 16 bit implementations 1 1 Reference Material Refer to the S1D13503 Hardware Functional Specification X18A A 001 xx for complete AC timing details This document makes no attempts to describe the operation of the ISA Bus please refer to the appropriate ISA Bu...

Page 244: ...ore either a serial terminal or monochrome display adapter is recommended as the primary console This section provides the necessary logic equations and settings to complete the interface between the S1D13503 and the 16 bit ISA Bus Note A PAL was used instead of discrete logic to reduce external component count Figure 1 16 Bit ISA Bus Implementation A 1 2 3 IOCS MEMCS AB0 19 BHE DB0 15 MEMW MEMR I...

Page 245: ...19 decoded internally to S1D13503 MEMCS REFRESH Note The MSBs of the address A23 A20 need not be externally decoded if using SMEMW and SMEMR as they will only assert on addresses 1Mb 2 2 Additional Discrete Logic Description 1 As shown in Figure 1 the 74LS688 is configured as a memory decoder with valid addresses between 0C0000h and 0DFFFFh This provides the MEMCS16 signal allowing for 16 bit memo...

Page 246: ...lowing exceptions Memory Interface AUX 1 bit 1 0 for 16 bit memory interface Note This bit is forced 0 when 16 bit CPU Interface is selected through VD0 on power up RAMS AUX 1 bit 0 this bit is ignored in 16 bit memory configurations All other registers are dependent on display type resolution color and mode of operation see Functional Specification for details Downloaded from Elcodis com electron...

Page 247: ...egment Note The 74LS00 is simply used to detect the B segment and invalidate the MEMCS input Note This memory configuration may conflict with a VGA card installed on the same bus therefore either a serial terminal or monochrome display adapter is recommended as the primary console This section provides the necessary settings to complete the interface between the S1D13503 and the 8 bit ISA Bus Sinc...

Page 248: ...uiring a 1 state see below 1 VD15 VD13 101 memory decoding for locations A segment 2 VD12 VD4 110000000 I O decoding for locations 1100000000b 1100000001b 3 VD3 0 No byte swap of high and low bytes 4 VD2 0 ISA Bus interface i e non MC68K interface 5 VD1 0 Indexed I O 6 VD0 0 8 bit bus interface Where 1 pull up with a 10K resistor 0 no pull up resistor 3 1 2 Register Setting All register settings a...

Page 249: ...se in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trade...

Page 250: ...son Research and Development Vancouver Design Center S1D13503 MC68340 Interface Considerations X18A G 004 04 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 251: ...e Date 01 01 30 X18A G 004 04 Table of Contents 1 INTRODUCTION 5 1 1 Reference Material 5 2 MC68340 MPU INTERFACE 6 2 1 MC68340 Setup 6 2 2 PAL Equations 7 2 3 S1D13503 Default Setup 7 List of Figures Figure 1 MC68340 MPU Interface Block Diagram 6 Downloaded from Elcodis com electronic components distributor ...

Page 252: ...son Research and Development Vancouver Design Center S1D13503 MC68340 Interface Considerations X18A G 004 04 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 253: ...h the use of minimal external circuitry This application note describes the interface between the S1D13503 and the 16 bit MC68340 microcontroller 1 1 Reference Material Refer to the S1D13503 Hardware Functional Specification X18A A 001 xx for complete AC timing details This document makes no attempts to describe the operation of the MC68340 microcontroller please refer to the appropriate MC68340 d...

Page 254: ...ing of the I O with starting address at 00000000h and 128Kbytes of display memory with starting address 00020000h are also used 1 CS3 with 256kbyte block size starting address at 00000000h and ending address at 0003FFFFh 2 External DSACK1 response 16 bit port 3 Don t care Function Codes and with CPU space access 4 Both read and write accesses are allowed Settings for the Address Mask register and ...

Page 255: ...itions 1 16 bit or 32 bit cycle i e SIZ0 0 2 8 bit cycle with odd byte access i e SIZ0 1 and A0 1 BHE SIZ0 A0 2 3 S1D13503 Default Setup Configuration Options 1 VD15 VD13 001 memory decoding for locations 20000h 3FFFFh 2 VD12 VD4 000000xxx I O decoding for locations 0000000000b 0000001111b 3 VD3 1 byte swap of high and low bytes 4 VD2 1 MC68K interface 5 VD1 1 direct mapping I O 6 VD0 1 16 bit bus...

Page 256: ...son Research and Development Vancouver Design Center S1D13503 MC68340 Interface Considerations X18A G 004 04 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 257: ... use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other tra...

Page 258: ... Research and Development Vancouver Design Center S1D13503 LCD Panel Options Memory Requirements X18A G 005 05 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 259: ...TION EQUATIONS 6 2 1 Example 6 2 1 1 Input Clock Requirement Calculation 6 2 2 SRAM Size and Access Time Requirements 7 2 2 1 SRAM Size 7 2 2 2 SRAM Access Time 7 3 CONCLUSIONS 7 4 IMPLEMENTATION 8 4 1 16 Bit Display Memory Interface 8 4 1 1 Configuration Options 8 4 1 2 Register Settings 9 List of Figures Figure 1 16 Bit Memory Configuration Example 8 Downloaded from Elcodis com electronic compon...

Page 260: ... Research and Development Vancouver Design Center S1D13503 LCD Panel Options Memory Requirements X18A G 005 05 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 261: ...nd number of colors gray shades all determine the memory and input clock requirements This application note describes the equations used to determine the various parameters An example resolution and desired frame rate will be selected and used to determine the remaining variables 1 1 Reference Material Refer to the S1D13503 Hardware Functional Specification X18A A 001 xx for complete AC timing det...

Page 262: ...t Clock Requirement Calculation For a frame rate of 70Hz the input clock or pixel clock frequency can be calculated as following fOSC input clock Where DHNDP is Default Horizontal Non Display Period in term of pixels DHNDP 16 pixels in gray shade display modes and DHNDP 32 pixels in BW display mode and in color display modes Where PHNDP is Programmable Horizontal Non Display Period in term of pixe...

Page 263: ...Access Time To support 256 color modes the S1D13503 must be configured to support a 16 bit data path into display memory SRAM For 16 bit display memory interface the required SRAM access time must be SRAM Access time 1 fOSC 40nsec 3 3v specification Therefore using a 6 0 Mhz input clock SRAM access time must be 127 ns Note For a detail description of the SRAM access time see section 9 2 of the S1D...

Page 264: ...ne 64Kx16 byte SRAM with 120ns access time will be used for this example Figure 1 16 Bit Memory Configuration Example 4 1 1 Configuration Options VD0 pull up with a 10K resistor for 16 bit bus interface Other option settings are not related to this implementation S1D13503 VWE VD0 7 VD8 15 VCS0 VCS1 VA0 15 SRAM WE UB LB A0 15 I O 1 8 I O 9 16 320x240 Color LCD UD0 3 LD0 3 YD LP XSCL 6 0MHz OSC1 64K...

Page 265: ...ress at 0000h with AUX 6 AUX 8 xxxx xxxx don t care when not using split screen AUX 9 xxxx xxxx don t care when not using split screen AUX A 1110 1111 together with AUX B bit1 0 should be the same as or larger than AUX 5 bit1 0 and AUX B xxxx xx00 AUX 4 when not using split screen AUX D 0000 0000 no virtual screen x don t care A sample of values for the Look Up Table to produce 256 colors is shown...

Page 266: ...n Research and Development Vancouver Design Center S1D13503 LCD Panel Options Memory Requirements X18A G 005 05 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 267: ... in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other tradema...

Page 268: ...e 2 Epson Research and Development Vancouver Design Center S1D13503 S1D13502 Comparison X18A G 008 04 Issue Date 01 01 30 THIS PAGE LEFT BLANK Downloaded from Elcodis com electronic components distributor ...

Page 269: ...ing external logic All other features not mentioned above are supported by both controllers See the S1D13503 Hardware Functional Speci fication X18A A 001 xx and the S1D13502 Hardware Functional Specification X16 SP 001 xx for further details Feature S1D13503 S1D13502 Color 4 16 256 colors Not available Monochrome Black and White 4 16 Gray Shades Not available 4 16 Gray Shades Display Data Formats...

Page 270: ...on these registers AUX 01h bit 2 LCD Data Width bit 0 bit 3 Gray Shade Color AUX 03h bit 1 Color Mode bit 2 BW 256 Colors bit 3 LCD Data Width bit 1 AUX 0Ch bit 0 7 Horizontal Non Display Period AUX 0Eh bit 4 ID Bit RGB Index Bit 0 bit 5 ID Bit RGB Index Bit 1 bit 6 Green Bank Bit 0 bit 7 Green Bank Bit 1 AUX 0Fh bit 4 Blue Bank Bit 0 bit 5 Blue Bank Bit 1 bit 6 Red Bank Bit 0 bit 7 Red Bank Bit 1...

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