PROGRAMMING
SINUS K
MANUAL
6/
226
0.2.
FIGURES
Figure 1: Digital input control modes ....................................................................................................................... 7
Figure 2: Connecting a relay to the OPEN COLLECTOR output............................................................................... 15
Figure 3: Parameters relating to auxiliary input processing...................................................................................... 17
Figure 4: Parameters relating to main reference processing. ................................................................................... 20
Figure 5: Block diagram of main reference processing for IFD SW........................................................................... 22
Figure 6: Block diagram of main reference processing for VTC SW. ........................................................................ 23
Figure 7: Parameters relating to the voltage/frequency pattern................................................................................ 24
Figure 8: Carrier frequency based on output frequency........................................................................................... 27
Figure 9 Carrier frequency with the........................................................................................................................ 27
Figure 10: Output frequency and motor rpm during speed searching (C55 = [YES] or C55 = [YES A]) activated by the
ENABLE command. t
OFF
< t
SSdis
(C56) or C56 = 0. .......................................................................................... 29
Figure 11: Frequency, rpm of the inverter motor during speed searching (power off, C55 =[YES A]) due to the
adjustment of the ENABLE command. t
1
+ t
2
< t
SSdis
(C56) or C56 = 0. ........................................................... 30
Figure 12: Output frequency, rpm, inverter locked, reset and ENABLE commands during speed searching due to an
alarm trip (C55 = [YES] or C55 = [YES A]). t
OFF
< t
SSdis
(C56) or C56 = 0........................................................ 31
Figure 13: Output frequency, rpm, inverter condition, power supply, reset and ENABLE commands when speed
searching is due to an alarm reset and to voltage removal from the inverter (C55 = [YES A]). t
1
+ t
2
< t
SSdis
(C56)
or C56 = 0................................................................................................................................................... 32
Figure 14: Equivalent circuit of the asynchronous machine..................................................................................... 34
Figure 15: Output frequency/speed and DC bus voltage of the inverter (V
DC LINK
) in case of mains failure with a higher
(a) or shorter (b) duration than the motor stop time......................................................................................... 36
Figure 16: Output frequency/speed and DC braking current when the DC BRAKING AT STOP function is enabled.... 37
Figure 17: Output frequency/speed and braking DC current when the DC BRAKING AT START function is active....... 38
Figure 18: Output frequency and braking direct current when the DC braking command is activated. ...................... 40
Figure 19: Output frequency and braking DC when the DC braking holding function is active.................................. 41
Figure 20: Motor heating with two different, constant current values (I01 and I02) and pick–up current It of the
protection with respect to the frequency/speed depending on the configuration of parameter C70 (IFD SW) or
C65 (VTC SW)............................................................................................................................................... 42
Figure0 21: Prohibit frequency/speed ranges. ........................................................................................................ 43
Figure 22: PID regulator block diagram (common section)...................................................................................... 46
Figure 23: PID regulator block diagram (relating to IFD SW only)............................................................................ 47
Figure 24: PID regulator block diagram (relating to VTC SW only)........................................................................... 47
Figure 25: Digital output programming with “REFERENCE LEVEL” programmed P60-P62 ......................................... 82
Figure 26: MDO with P60-P62 programmed as 1-FREQUENCY SPEED LEVEL 2-FORWARD RUNNING, 3-REVERSE
RUNNING .................................................................................................................................................... 82
Figure 27: MDO with P60-P62 programmed as Fout/Nout ok................................................................................. 83
Figure 28: MDO with P60-P62 programmed as current level .................................................................................. 83
Figure 29: MDO with P60-P62 programmed as “PID ERROR” ................................................................................. 84
Figure 30: MDO with P60-P62 programmed as “PID MAX OUT.............................................................................. 84
Figure 31: MDO with P60-P62 programmed as “PID OUT MIN”............................................................................. 85
Figure 32: MDO with P60-P62 programmed as “FB MAX”...................................................................................... 85
Figure 33: MDO with P60-P62 programmed as “FB MIN” ...................................................................................... 86
