Elan Digital Systems Ltd.
23
HD717 USER’S
GUIDE
IPR0
SCCIntPending: Reads back as a ‘1’ when
there is an interrupt pending from the SCC.
The SCC must be set to use a software
INTACK mode (WR9) so that the SCC’s
interrupt line is de-asserted when RR2 is
accessed to determine the reason for the SCC
interrupt.
IPR4
RXFIFOIntPending: : Reads back as a ‘1’
when there is an interrupt pending due to the
RX 4K FIFO rising above half full. The
interrupt is cleared by a PC read from the RX
4K FIFO.
MSR3
RXFIFOEmpty: Status of the RX 4K FIFO’s
empty flag (active low).
MSR4
RXFIFOHalf: Status of the RX 4K FIFO’s half
full flag (active low).
MSR5
RXFIFOFull: Status of the RX 4K FIFO’s full
flag (active low).
See the SCC TX section for details on accessing the SCC’s registers
whilst receiving data into the RX 4K FIFO.
3.1.6 RS485 SUPPORT (Issue 2(+) HD717 & HD712,713 Cards Only)
The HD717 uses RS422/485 line drivers for all signals associated
with the SCC. To allow a bussed (half duplex) TX/RX scheme such
as found in RS485 systems, a tri-state control is used to disable the
TXD driver so that another “talker” can driver the bus. This bit must
be manipulated by software to affect a co-operative bus mastering
system. Connections external to the card are needed to link TXD+
to RXD+ and TXD- to RXD-.
REGISTER BIT
FUNCTION
SCR3
n422TXEN. This bit set low is used to enable
the RS422/485 driver for the TXD+/- signals
(pins 1 & 2). Setting this bit high tri-states the
signals. Reset state of this bit is LOW .
