ELAN DIGITAL SYSTEMS LTD. HD717 User Manual Download Page 45 | Manualshive

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Elan Digital Systems Ltd.

45

HD717 USER’S

GUIDE

4.10 LBG (SUB REG 1)

BIT

FUNCTION

RESE
T
STAT
E

WRITE

READ

0

LBG

LBG

0

1

LBG

LBG

0

2

LBG

LBG

0

3

LBG

LBG

0

4

LBG

LBG

0

5

LBG

LBG

0

6

LBG

LBG

0

7

LBG

Set this bit high to enable the

LRD Baud Gen

LBG

0

This register is the divider used to set the Low Rate Data baud
rate. Bit7 acts as a master enable for the baud generator.

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Summary of Contents for HD717

Page 1: ...ER S GUIDE ALSO COVERS HD712 HD713 REVISION HISTORY ISSUE PAGES DATE NOTES 1 59 11 04 97 FIRST ISSUE 2 60 28 04 97 NEW FEATURES 3 60 09 09 97 SCC DATA CLK TIMING NOTE p15 4 58 28 01 98 SIMPLIFY PCCARD...

Page 2: ...DURE 17 3 1 5 SCC RECEIVE PROCEDURE 21 3 1 6 RS485 SUPPORT Issue 2 HD717 HD712 713 Cards Only 23 3 2 LOW RATE DATA 24 3 2 1 TRANSMIT 24 3 2 2 RECEIVE 28 3 3 HANDLING INTERRUPTS 31 3 4 USING THE DIGITA...

Page 3: ...4 13 DIR SUB REG 4 47 4 14 SCR SUB REG 5 48 4 15 MSR READ ONLY SUB REG 6 49 4 15 IMR READ ONLY SUB REG 7 50 5 HARDWARE SPECIFICATION 51 5 1 PINOUT 51 5 2 POWER CONSUMPTION 53 5 3 MECHANICAL 53 5 4 EN...

Page 4: ...described herein neither does it convey any licence under its patent rights not the rights of others Elan products are not authorised for use as components in life support services or systems Elan sho...

Page 5: ...5MBits s on Iss2 01 HD717 13 3 25 1 625 0 8125MBits s on HD713 RS422 interface drivers and receivers for SCC Issue 2 HD717 and all HD712 713 cards have support for RS485 shared data bus scheme 4Kx8 t...

Page 6: ...way the SCC operates on the HD717 is that the data for TX and RX is buffered by 4096 x 8 FIFOs On an ISA card it is common to use the SCC in DMA mode where two DMA channels are used one for TX and on...

Page 7: ...2 1 1 Functional Block Diagram of SCC FIFOs 2 2 LOW RATE DATA INTERFACES The HD717 provides inputs and outputs for two of the common ARINC 717 serial data protocols namely Bipolar Return to Zero and H...

Page 8: ...1 1 0 0 0 5V 5V 0V 5V 5V 0V LINE A to GND LINE B to GND BIT CELL As can be seen there is sufficient clocking information in both waveforms to allow complete asynchronous reception without the source c...

Page 9: ...ve loads i e very long cables 2 3 DIGITAL I O INTERFACE 8 Digital I O drivers are provided on the HD717 to use as general purpose control outputs and or status monitoring inputs The I O pins are logic...

Page 10: ...ect or deposit data to the FIFOs as required The SCC control registers use a two access process The first access to IOBASE 0 is a write which contains the pointer to the SCC internal register to read...

Page 11: ...sible REGISTER REQUIRED STATE binary MSB LSB 76543210 WR1 11111x01 F9h Ext status MIE ON TX int en OFF RX int on special conditions DMA on RX ON Select RX DMA mode Master RX DMA en ON 1 1 Set to on wh...

Page 12: ...RX clock RTxC is NOT a crystal osc NB The TRxC pin on the SCC is wired to a logic driver circuit the output of the TX clock select MUX on the card Therefore it MUST be set to an input on the SCC if S...

Page 13: ...S GUIDE WR14 xxxxx1xx x4h Select TX DMA mode WR15 11000101 C5h Use to access WR7 or WR7 No zero count int on BRGen Enable status FIFO in SCC No DCD int No SYNC hunt int No CTS int Enable int on TX und...

Page 14: ...selected SCS6 7 SCS1 SCS 1 0 00 4MHz default SCS 1 0 01 2MHz SCS 1 0 10 1MHz SCS 1 0 11 0 5MHz SCS2 TRxCEn This bit allows the HD717 driver connected to the SCC s TRxC pin to be tri stated When set h...

Page 15: ...K pin on the SCC This allows greater flexibility in the baud rates available when the SCC is used in async mode Note that when SCS5 is low only one of two states can be selected for either the TRxC or...

Page 16: ...ignificant extra skew between clock and data is added Typically 0ns of setup and 50ns of hold are required at the SCC in receive relative to the RX clock edges In transmit the delay between TX clock e...

Page 17: ...greater than 4K The following flow diagram summarises the steps to transmit data DISABLE HD717 TX DMA CONFIGURE SCC AS REQUIRED WITH TX DMA ENABLED AND TX ENABLED LOAD TX 4K FIFO WITH TX DATA ENABLE...

Page 18: ...ciency the ISR can also inspect the TX 4K FIFO Full Half Full and Empty flags This would allow the ISR to decide to write more data if required in an attempt to better fill the TX 4K FIFO If this tech...

Page 19: ...them IMR3 MaskTXFIFOHInt Set to 1 to mask interrupts from the TX 4K FIFO as it falls below half full Set to 0 to allow them IMR5 MaskTXFIFOEInt Set to 1 to mask interrupts from the TX 4K FIFO as it fa...

Page 20: ...the TX 4K FIFO s half full flag active low MSR2 TXFIFOFull Status of the TX 4K FIFO s full flag active low While the HD717 is transmitting data from the TX 4K FIFO via the SCC the PC can still access...

Page 21: ...LE HD717 RX DMA The above process could generate an interrupt request for three reasons 1 The SCC signals that it has completed the message EOM i e message is ready in the RX 4K FIFO 2 The SCC signals...

Page 22: ...getting stuck trying to empty an ever filling FIFO In such a case use only the single 2K block read and then exit the ISR HD717 control status registers that relate to an SCC RX are listed below REGI...

Page 23: ...ull Status of the RX 4K FIFO s full flag active low See the SCC TX section for details on accessing the SCC s registers whilst receiving data into the RX 4K FIFO 3 1 6 RS485 SUPPORT Issue 2 HD717 HD71...

Page 24: ...s ARINC 717 An interrupt is generated each time the holding register is moved into the p to s converter This means that the interrupt frequency will be baud rate 12 interrupts sec Software must ensure...

Page 25: ...M1 are on Pins 19 20 HVDOUTa b The baud rate is set using a programmable divider in the HD717 The formula for the baud rate is given by LRD Baud Rate 16x106 868 LBG 0x7F 1 Hz where LBG is the 8 bit nu...

Page 26: ...complete the ISR must deposit 12 bit words into the holding register every LRD TX interrupt The ISR must use the IRQInService bit to ensure that other interrupts received while in the ISR is executin...

Page 27: ...set the TX and RX encoding mode used for LRD PCR7 LRDTXEn Set to 1 to allow data from the p to s converter to drive the LRD output driver circuits Set to 0 to force the LRD output drivers to send all...

Page 28: ...e interrupt is cleared when the high byte nibble of the 12 bit word is read from the holding register NB the top 4 bits of the high byte read as zero Data is received Least Significant Bit first The e...

Page 29: ...ting that an IRQ is being serviced by software Set the bit to 1 to lock the IRQ state as the first action of the ISR Return it to 0 as the last action of the ISR this may immediately re activate the I...

Page 30: ...c condition has been received in FM0 1 modes In other modes it always reads as 1 A point worthy of note is that if you connect the LRD TX and RX circuits together as a test of operation the RX words w...

Page 31: ...the ISR All interrupts except the SCC interrupt are latched inside the HD717 A power on or soft reset will de assert the interrupts The SCC may however produce interrupts during configuration You are...

Page 32: ...ov cx 2048 num bytes to copy les di DWORD PTR RXBuff pointer to data mov DX IOBase base IO address of HD717 add DX RXFIFOReg offset to RX FIFO rep insb copy the block from the FIFO RXBytesGot 2048 adj...

Page 33: ...rror SCCErrorTrap PARITY else if RR1 0x20 RX overrun error SCCErrorTrap RXOVERRUN else if RR1 0x80 End of RX frame if RR1 0x40 CRC error at end of frame SCCErrorTrap CRCERROREOF RXBytes 0 Get data fro...

Page 34: ...hat unmasking an interrupt via the IMR register actually removes the clear from the flip flop holding the interrupt This means that unmasking an interrupt is different to using the MIRQEn bit in the P...

Page 35: ...al I O pins are read back via the DIDI 7 0 register Again the bit for bit correspondence applies between the DIOPin number and the regsiter bit number The directions of the pins is controlled via the...

Page 36: ...fter a reset The only valid CONFIG value is 01d Bit7 of the COR acts as a soft reset when set the reset does not clear bit7 but a subsequent write to the config register to return bit 7 to zero should...

Page 37: ...UT DATA REGISTER 4 DIR 4 0 DIGITAL I O PIN DIRECTION REGISTER DIR 4 0 DIGITAL I O PIN DIRECTION REGISTER 5 SCR 7 0 SECONDARY CONTROL REGISTER SCR 7 0 SECONDARY CONTROL REGISTER 6 MSR 7 0 MISCELLANEOUS...

Page 38: ...L 7 SCC CONTROL SCC CONTROL This port gives access to the SCC s internal control registers i e WR0 15 and RR0 15 4 2 SCC DATA IOBASE 1 BIT FUNCTION RESE T STAT E WRITE READ 0 SCC TX DATA SCC RX DATA 1...

Page 39: ...MASK LRDRXIntPending IPR LRDRXIntPending 0 3 IMR MASK TXFIFOHIntPending IPR TXFIFOHIntPending 0 4 IMR MASK RXFIFOIntPending IPR RXFIFOIntPending 0 5 IMR MASK TXFIFOEIntPending IPR TXFIFOEIntPending 0...

Page 40: ...Rate Data This port is the low byte read port for the RX Low Rate Data 4 5 LRD RX HI READ TX HI WRITE IOBASE 4 BIT FUNCTION RESE T STAT E WRITE READ 0 LRDTXLO LRDRXLO 0 1 LRDTXLO LRDRXLO 0 2 LRDTXLO L...

Page 41: ...This port is the data read write register used to access the sub register pointed to by the SUB REG IDX IOBASE 6 To access a SUB REG load the SUB REG IDX with the number of the SUB REG Then read or wr...

Page 42: ...Elan Digital Systems Ltd 42 HD717 USER S GUIDE...

Page 43: ...FIFO 2 TX 4K FIFO RX 4K FIFO 3 TX 4K FIFO RX 4K FIFO 4 TX 4K FIFO RX 4K FIFO 5 TX 4K FIFO RX 4K FIFO 6 TX 4K FIFO RX 4K FIFO 7 TX 4K FIFO RX 4K FIFO This port is the TX 4K FIFO which feeds the SCC wi...

Page 44: ...NCTION RESE T STAT E WRITE READ 0 PCR MIRQEn PCR 0 1 PCR IRQInService PCR 0 2 PCR TXDMAEn PCR 0 3 PCR RXDMAEn PCR 0 4 PCR LRDMode0 PCR 0 5 PCR LRDMode1 PCR 0 6 PCR LRDMode2 PCR 0 7 PCR LRDTXEn PCR 0 T...

Page 45: ...T STAT E WRITE READ 0 LBG LBG 0 1 LBG LBG 0 2 LBG LBG 0 3 LBG LBG 0 4 LBG LBG 0 5 LBG LBG 0 6 LBG LBG 0 7 LBG Set this bit high to enable the LRD Baud Gen LBG 0 This register is the divider used to s...

Page 46: ...te select bit 0 SCS 0 1 SCS Clock rate select bit 1 SCS 0 2 SCS TRxCEn RESERVED 0 3 SCS EdgeSel write 0 SCS 0 4 SCS SCCPClkEn SCS 0 5 SCS SCCTRClkEn Also performs OSC selection on HD712 713 Iss2 01 HD...

Page 47: ...egister is the read write port for the DIOPin data DIDO is the data written to control the pins set as outputs DIDI is the actual state of all 8 DIOPins 4 13 DIR SUB REG 4 BIT FUNCTION RESE T STAT E W...

Page 48: ...AT E WRITE READ 0 SCR NONSync SCR 0 1 SCR CLRSync SCR 0 2 RESERVED Write 0 RESERVED 0 3 SCR n422TXEN SCR 0 4 RESERVED Write 0 RESERVED 0 5 RESERVED Write 0 RESERVED 0 6 RESERVED Write 0 RESERVED 0 7 R...

Page 49: ...TION RESE T STAT E WRITE READ 0 MSR TX 4K FIFO EMPTY BAR 1 MSR TX 4K FIFO HALF FULL BAR 2 MSR TX 4K FIFO FULL BAR 3 MSR RX 4K FIFO EMPTY BAR 4 MSR RX 4K FIFO HALF FULL BAR 5 MSR RX 4K FIFO FULL BAR 6...

Page 50: ...ER S GUIDE 4 15 IMR READ ONLY SUB REG 7 BIT FUNCTION RESE T STAT E WRITE READ 0 IMR SCC 1 IMR LRD TX 2 IMR LRD RX 3 IMR TX FIFO 4 IMR RX FIFO 5 RESERVED 6 RESERVED 7 RESERVED This register is the read...

Page 51: ...INPUT 12 RXCLKIN SCC RX RS422 EXTERNAL CLOCK INPUT 13 GND 0V 14 GND 0V 15 HVDOUTa LOW RATE DATA TX FOR FM0 1 MODES LINE A 16 HVDOUTb LOW RATE DATA TX FOR FM0 1 MODES LINE B 17 BRZOUTa LOW RATE DATA TX...

Page 52: ...Elan Digital Systems Ltd 52 HD717 USER S GUIDE PIN 1 PIN 32 TOP OF CARD...

Page 53: ...HUMIDITY 80 NON CONDENSING TEMP 0 50 C AMBIENT 5 5 LOOP BACK CONNECTIONS FOR TEST SOFTWARE For the 717test program the following direct links should be made PIN 1 PIN 7 PIN 2 PIN 8 PIN 3 PIN 11 PIN 4...

Page 54: ...ifies greatly the enumeration process and configuration management task for your application The driver is supplied on the diskette provided Please refer to PCCARDGO DOC for further information 6 2 C...

Page 55: ...excessive current from Vcc The limit is shown in the pinout table Doing so will adversely effect the HD717 s performance and could cause damage The 32 way IO connector is quite delicate Don t stress...

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