Elan Digital Systems Ltd.
30
HD717 USER’S
GUIDE
SCR0
NONSync: Setting this bit high allows bits
received prior to a known sync condition, to
enter the s-to-p converter and so cause
interrupts every 12-bits (if the CLRSync bit is
low). This is useful for debugging. If the bit is
low, the receiver will not generate any
interrupts until 12-bits after and including a
known sync condition has been received (i.e.
the syncable bit IS captured)
SCR1
CLRSync: This bit acts as a direct reset to the
flip-flop in the HD717 that stores the status for
the known sync condition having been
received. Setting it to ‘0’ ‘1’ ‘0’ will reset the
receiver and force it back to a condition where
sync is NOT assumed. This is like placing the
receiver back into “hunt” mode.
MSR6
LRDRXSync: This bit reads as ‘1’ when a
known sync condition has been received in
FM0/1 modes. In other modes it always reads
as ‘1’.
A point worthy of note is that if you connect the LRD TX and RX
circuits together as a test of operation, the RX words will apear in
the LRD RX holding register delayed relative to the TX data. The
amount of delay depends on how the software starts the TX and RX
processes running. Do not expect the RX data WORDs to be on the
same “bit-alignment” as the transmitted words. The bit-by-bit data
stream will be preserved but the WORD “boundaries” are unlikely to
match (this is intrinsic in the nature of the asynchronous data
transport mechanism). Also expect the FM and BRZ modes to show
different relative delays.
The HD717’s FM decoding can tolerate duty cycle errors of up to
5% i.e. 45% to 55% duty cycle (for an FM encoded bit) and
additionally up to 2% error in the nominal bit rate.
BipolarRZ is essentially unrestricted in its capability, i.e. the baud
rate is “self determined” (as its is totally recovered from the data).
