Elan Digital Systems Ltd.
14
HD717 USER’S
GUIDE
3.1.3 SCC TX/RX CLOCK SELECTION
As well as being able to select various clock sources for the SCC via
WR11, the HD717 also pre-muxes both the TX and RX clocks to
allow even greater flexibility on how the card is used in synchronous
systems. Refer to Figure 2.1-1 for a block diagram showing the
clock routing.
Various HD717 control registers effect the clock selection, they are
summarised here:
REGISTER BIT
FUNCTION
SCS0
Together form a 2-bit selection code for the
frequency applied to the SCC’s TRxC & RTxC
pins when the HD717 derived clock is selected
(SCS6/7):
SCS1
SCS[1:0]=00: 4MHz (default)
SCS[1:0]=01: 2MHz
SCS[1:0]=10: 1MHz
SCS[1:0]=11: 0.5MHz
SCS2
TRxCEn. This bit allows the HD717 driver
connected to the SCC’s TRxC pin to be tri-
stated. When set high, the HD717 drives the
SCC. When low, the SCC can be programmed
to output on its TRxC pin if required e.g to
output its internal baud generator or DPLL clk.
SCS3
EdgeSel. This bit allows the HD717 clock
divider to use either the +ve or -ve edge of the
master 16MHz clock supplying the SCC. The
default state is 0: +ve edge. This bit should be
left at the default state.
SCS4
SCCPClkEn. This bit acts as a master enable
for the SCC’s master oscillator (PCLK). The
default state is 0: DISABLE PCLK. When
enabled, the SCC is clocked at 16MHz. UNTIL
THIS BIT IS SET, NO OPERATION WITH
THE SCC WILL BE POSSIBLE.
