Elan Digital Systems Ltd.
26
HD717 USER’S
GUIDE
The following procedure should be used when enabling LRD
Transmit, to ensure that no erroneous data is transmitted:
MASK LRD TX
INTERRUPT
⇓⇓
DISABLE LRD TX
⇓⇓
WRITE 000h TO
LRD TX HOLDING
REGISTER
⇓⇓
SET LRD BAUD RATE AS
REQUIRED
⇓⇓
ENABLE LRD TX
⇓⇓
WAIT FOR TWO
WORD PERIODS
MINIMUM
⇓⇓
UNMASK LRD TX
INTERRUPT
⇓⇓
⇓⇓
⇓⇓
Once this procedure is complete, the ISR must deposit 12-bit words
into the holding register every LRD TX interrupt. The ISR must use
the IRQInService bit to ensure that other interrupts received while in
the ISR is executing are properly dealt with. See the section on
interrupt handling for details.
Note that unmasking an interrupt via the IMR register actually
removes the clear from the flip flop holding the interrupt. This
means that unmasking an interrupt is different to using the MIRQEn
bit in the PCR to “block” interrupts. The above procedure requires
interrupts to be unmasked.
