Elan Digital Systems Ltd.
27
HD717 USER’S
GUIDE
HD717 control / status registers that relate to LRD TX are listed
below:
REGISTER BIT
FUNCTION
PCR0
MIRQEn: Set to ‘1’ to allow any interrupt
through to the PC
PCR1
IRQInService: Use this bit in the ISR routine
to lock the IRQ state, so indicating that an IRQ
is being serviced by software. Set the bit to ‘1’
to lock the IRQ state as the first action of the
ISR. Return it to ‘0’ as the last action of the
ISR (this may immediately re-activate the IRQ
to the PC).
PCR[6:4]
LRDMode: Three bit code to set the TX and
RX encoding mode used for LRD.
PCR7
LRDTXEn: Set to ‘1’ to allow data from the
p-to-s converter to drive the LRD output driver
circuits. Set to ‘0’ to force the LRD output
drivers to send all ‘0’s.
IMR1
MaskLRDTXInt: Set to ‘1’ to mask interrupts
from the LRD TX function. Set to ‘0’ to allow
them.
IPR1
LRDTXIntPending: : Reads back as a ‘1’ when
there is an interrupt pending due to the LRD
transmitter copying the TX holding register to
the p-to-s converter. The interrupt is cleared by
a PC write to the high nibble of the holding
register.
LBG[7:0]
LRD Baud rate generator divider.
LRDTXLO[7:0]
Low byte of 12-bit TX holding register
LRDTXHI[3:0]
High nibble of 12-bit TX holding register (top
four bits of 8-bit register are “don’t care”)
