Elan Digital Systems Ltd.
16
HD717 USER’S
GUIDE
Figure 3.1.3-1 Clock Routing Internal to HD717
Note that the SCC’s TRxC and RTxC pins are buffered to RS422
levels and driven off card as T/- (Pins 3 & 4: this is
TRxC), and as R/- (Pins 9 & 10: this is RTxC).
It is vital for correct opperation that the timings for the TX/RX clock
and data follow the requirements laid down in the Zilog SCC data
sheets. In a synchronous system there must be sufficient setup and
hold time for the data relative to the clock. In the external clock
case, the HD717 passes clock and data through the same type of
RS422 receiver / transmitter chips. This means that no significant
extra skew between clock and data is added. Typically, 0ns of setup
and 50ns of hold are required at the SCC in receive relative to the
RX clock edges. In transmit, the delay between TX clock edges and
data changing is 80ns.
Be aware that some combinations of data and clock
will not work
reliably when used in a loop-back test mode. For example, clocking
the TX and RX clocks from the same source (internal to the card)
and sending the TX data “out” of the card through two pieces of
wire and back “in” to the card may not work properly at 2 or 4MHz.
This is because the RX data is grossly skewed relative to the RX
clock because the data has passed through two RS422 transcievers
but the clock has not.
SCS6
SCS7
SCS5
D0
D1
D2
D3
Y
S1
S0
1
2
3
4
6
7
5
D0
D1
D2
D3
Y
S1
S0
1
2
3
4
6
7
5
Y
1
TXCLKIN
RXCLKIN
TXCLK
RXCLK
16MHZ
16MHZ
0.5/1/2/4MHz
