Elan Digital Systems Ltd.
22
HD717 USER’S
GUIDE
bytes in one block (remember that the IRQ occurs when the RX 4K
FIFO goes above half full). For even greater efficiency, the ISR can
also inspect the RX 4K FIFO Full, Half Full and Empty flags. This
would allow the ISR to decide to read more data if required in an
attempt to better empty the RX 4K FIFO. If this technique is used
remember that once the initial 2K block has been read by the ISR,
every subsequent byte read must made conditional on the Empty flag
being high (else the ISR could read “beyond” empty). At high data
rates, this extra flag check could lead to the ISR emptying the FIFO
more slowly than it is being filled by the SCC which could
ultimately lead to a FIFO full condition and the ISR getting “stuck”
trying to empty an ever filling FIFO ! In such a case, use only the
single 2K block read and then exit the ISR.
HD717 control / status registers that relate to an SCC RX are listed
below:
REGISTER BIT
FUNCTION
PCR0
MIRQEn: Set to ‘1’ to allow any interrupt
through to the PC
PCR1
IRQInService: Use this bit in the ISR routine
to lock the IRQ state, so indicating that an IRQ
is being serviced by software. Set the bit to ‘1’
to lock the IRQ state as the first action of the
ISR. Return it to ‘0’ as the last action of the
ISR (this may immediately re-activate the IRQ
to the PC).
PCR3
RXDMAEn: Set to ‘1’ to allow the HD717 RX
DMA controller to honour SCC RX DMA
requests. The RX DMA controller will only
“run” if the RX 4K FIFO contains <4096 bytes
of data.
IMR0
MaskSCCInt: Set to ‘1’ to mask interrupts
from the SCC. Set to ‘0’ to allow them.
IMR4
MaskRXFIFOInt: Set to ‘1’ to mask interrupts
from the RX 4K FIFO as it rises above half full.
Set to ‘0’ to allow them.
