Elan Digital Systems Ltd.
29
HD717 USER’S
GUIDE
In FM0 and FM1 modes, the synchronisation can only be guaranteed
when a non-phase encoded bit has entered the receiver (i.e. a logic
‘0’ for FM1 and a logic ‘1’ for FM0). There are two bits that define
how the HD717 behaves prior to this synchronised state and one
status bit to determine when sync has been achieved. See below for
details.
HD717 control / status registers that relate to LRD RX are listed
below:
REGISTER BIT
FUNCTION
PCR0
MIRQEn: Set to ‘1’ to allow any interrupt
through to the PC
PCR1
IRQInService: Use this bit in the ISR routine
to lock the IRQ state, so indicating that an IRQ
is being serviced by software. Set the bit to ‘1’
to lock the IRQ state as the first action of the
ISR. Return it to ‘0’ as the last action of the
ISR (this may immediately re-activate the IRQ
to the PC).
PCR[6:4]
LRDMode: Three bit code to set the TX and
RX encoding mode used for LRD.
IMR2
MaskLRDRXInt: Set to ‘1’ to mask interrupts
from the LRD RX function. Set to ‘0’ to allow
them.
IPR2
LRDRXIntPending: : Reads back as a ‘1’ when
there is an interrupt pending due to the LRD
receiver copying the s-to-p converter to the RX
holding register. The interrupt is cleared by a
PC read from the high nibble of the holding
register.
LBG[7:0]
LRD Baud rate generator divider.
LRDRXLO[7:0]
Low byte of 12-bit RX holding register
LRDRXHI[3:0]
High nibble of 12-bit RX holding register (top
four bits of 8-bit register read as zero)
