DIGITAL-LOGIC MICROSPACE MSEP800, Technical User'S Manual

Page: 50 / 140

DIGITAL-LOGIC AG
MSEP800 Manual V1.0G
50
4.8 Memory & I/O Map
4.8.1 System Memory Map
The X86 CPU used as central processing unit on the MICROSPACE has a memory address space which is
defined by 32 address bits. Therefore, it can address 1 GByte of memory. The memory address MAP is as
follows:
CPU GEODE
Address:
Size: Function / Comments:
000000 - 09FFFFh 640 KBytes Onboard DRAM for DOS applications
0A0000 - 0BFFFFh 128 KBytes CGA, EGA, LCD Video RAM 128kB
0C0000 - 0C7FFFh
0C8000 - 0CFFFFh 32 KBytes
32 KBytes VGA BIOS
Free for user
0D0000 - 0DFFFFh 64 KBytes free for user
0E0000 - 0EBFFFh
0EC000 - 0EFFFFh 32 KBytes
16 KBytes Bios
BIOS extensions
0F0000 - 0FFFFFh 64 KBytes Core BIOS
100000 - 1FFFFFFh 31 MBytes DRAM for extended onboard memory
4.8.2 System I/O map
The following table details the legacy I/O range for 000h through 4FFh. Each I/O location has a read/write
(R/W) capability.
Note the following abbreviations:
---
Unknown or can not be determined.
Yes Read and write the register at the indicated location. No shadow required.
WO Write only. Value written can not be read back. Reads do not contain any useful information.
RO Read only. Writes have no effect.
Shw The value written to the register can not be read back via the same I/O location. Read back is
accomplished via a “Shadow” register located in MSR space.
Shw@ Reads of the location return a constant or meaningless value.
Shw$ Reads of the location return a status or some other meaningful information.
Rec Writes to the location are “recorded” and written to the LPC. Reads to the location return the
recorded value. The LPC is not read.