DIGITAL-LOGIC MICROSPACE MSEP800, Technical User'S Manual

Page: 108 / 140

DIGITAL-LOGIC AG
MSEP800 Manual V1.0G
108
12.2.2 Two digit 7-segment POST LED
After powerup during booting of the BIOS the Power-On-Self-Test (POST) code is displayed on the two digit
7-segment LED’s. Therefore the CPLD decodes this 8-bit hexadecimal code to the 7-segment common
anode code at I/O address 80 hex. To save about 0.6 Watt it is possible to power-off the LED’s.
POD80
POST
Code Register
I/O address
0080h
Type Write
only
Default value
0Bh
The LED display by default the CPLD
software version
0B hex => version 1.1 decimal
CPLD_CTRL
CPLD Control Register
I/O Address 0240h
Type Write only
Default Value NNNN NN0Nb
This register controls the power off switching of the two 7-segment LED’s, by default they are powered on.
Bit
Function Description
7:2,0 Not implemeted, reserved for future use
0 Power on
1 7-Segment LED power off
1 Power off
At the beginning of each POST routine, the BIOS outputs the test point error code to I/O address 80 hex.
Use this code during trouble shooting to establish at what point the system failed and what routine was being
performed.
If the BIOS detects a terminal error condition, it halts POST after issuing a terminal error beep code and
attempting to display the error code on upper left corner of the screen and on the port 80h LED display. It
attempts repeatedly to write the error to the screen. This may cause "hash" on some CGA displays.
If the system hangs before the BIOS can process the error, the value displayed at the port 80h is the last test
performed. In this case, the screen does not display the error code.
See List of POST- and beep codes in the diagnostic chapter of the manual.
D Q
[7:0]
SD[7:0]
Data Register
8-bit I/O 80h high / low
byte
D[1]
Q[1]
SD[2:0]
Control Register
1-bit I/O 240h
Power-off = 1