DIGITAL-LOGIC MICROSPACE MSEP800, Technical User'S Manual

Page: 42 / 140

DIGITAL-LOGIC AG
MSEP800 Manual V1.0G
42
4.6 CMOS RAM Map
Systems based on the industry-standard specification include a battery backed Real Time Clock chip.
This clock contains at least 64 bytes of non-volatile RAM. The system BIOS uses this area to store in-
formation including system configuration and initialization parameters, system diagnostics, and the time
and date. This information remains intact even when the system is powered down.
The BIOS supports 128 bytes of CMOS RAM. This information is accessible through I/O ports 70h and
71h. CMOS RAM can be divided into several segments:
Locations 00h - 0Fh contain real time clock (RTC) and status information
Locations 10h - 2Fh contain system configuration data
Locations 30h - 3Fh contain System BIOS-specific configuration data as well as chipset-specific
information
Locations 40h - 7Fh contain chipset-specific information as well as power management configuration
parameters
The following table provides a summary of how these areas may be further divided.
Beginning Ending Checksum Description
00h 0Fh No RTC and Checksum
10h 2Dh Yes System Configuration
2Eh 2Fh No Checksum Value of 10h - 2Dh
30h 33h No Standard CMOS
34h 3Fh No Standard CMOS - SystemSoft Reserved
40h 5Bh Yes Extended CMOS - Chipset Specific
5Ch 5Dh No Checksum Value of 40h - 5Bh
5Eh 6Eh No Extended CMOS - Chipset Specific
6Fh 7Dh Yes Extended CMOS - Power Management
7Eh 7Fh No Checksum Value of 6Fh - 7Dh