Digital Equipment DIGITAL Server 7100 1200, Service Maintenance Manual

Page: 44 / 162

SCU Features
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Menu Fields Settings Comments
2nd OPB CPU
Line Read Pre-
Fetch Disabled
Enabled
(1)
When enabled, allows the 2nd OPB’s PCI memory
read line commands to pre-fetch additional processor
cache lines.
CPU in order
queue depth 8
(1)
1
Allows you to select the depth of the processor in-
order-queue.
APIC & MP table Disabled
MPS 1.1
MPS 1.4
(1)
Applicable to single processor configurations only,
always enabled for Multi-Processing (MP) operating
system configurations. When set to MPS 1.1 or MPS
1.4, the processor’s Advanced Programmable
Interrupt Controller (APIC) is enabled, and the MP
table used by MP operating systems will be created.
Note: This parameter must be disabled for NetWare
3.12 single processor systems.
ECC interrupt Disabled
(1)
IRQ14, Shared
IRQ14, Non-Shared
IRQ15, Shared
IRQ15, Non-Shared
Enables the Error Correction Code (ECC) interrupt. If
enabled, you can select IRQ14 or IRQ15 as the ECC
interrupt. You can also define the IRQ as shared with
other devices, such as EISA or PCI devices.
GAT mode Enabled
(1)
Disabled
Should be enabled only when an ISA bus mastering
card is installed in the server. Disable it for all other
configurations.
System arbitration CPU Bus first
(1)
EISA Bus first
Full Rotation
This option controls the operating modes of the
server’s PCI arbiter. The arbiter controls the
arbitration priorities for EISA, PCI, and processor
buses.
(1)
Factory default setting