
pe_macro(1)
Message #33: The test attempts to fetch 0x5b6b7b8b using the
rfetch32
command. This word contains the result of that operation. The higher
order bits should remain zero.
Message #34: This is the higher order bits of the destination. All these
bits should remain zero.
Message #35: Each cluster of 3 bits represents the state of the fflag, the
rflag and the tflag after each stage of the test.
0
0 f
f
f
f
ff
r
r
r
r
r
t
t
t
t
t
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
After enable
After ropen
After rclose
After
After
rsend32
rfetch32
MPP_FIG_281
Messages #36–39: These words are comparable to words #31–34, except
they are from the unselected PEs. Normally, no data reaches these
destinations, and they remain at zero.
Message #40: This displays the flag bits from the unselected PEs which
should all remain at zero.
Message #41: The test attempts to send 0x5a6a7a8a using the
rsend64
command. This word contains the low order bits of that operation.
Message #42: This is the higher order bits of the destination.
Message #43: The test attempts to fetch 0x5b6b7b8b using the
rfetch64
command. This word contains the low order bits of that operation.
Message #44: This is the higher order bits of the destination.
Message #45: Each cluster of 3 bits represents the state of the fflag, the
rflag and the tflag after each stage of the test.
0
0 f
f
f
f
ff
r
r
r
r
r
t
t
t
t
t
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
After enable
After ropen
After rclose
After
After
rsend64
rfetch64
MPP_FIG_282
Messages #46–49: These words are comparable to words #41–44, except
they are from the unselected PEs. Normally, no data reaches these
destinations, and they remain at zero.
Message #50: This displays the flag bits from the unselected PEs which
should all remain at zero.
•
rt0g
: Router Open/Send And Fetch/Close Test — This test performs router
open/send and fetch operations. It disables all PEs except #0. The source and
destination is PE #0. It verifies that the correct data reaches the destination
and that the correct tflag, rflag and fflag is set after each operation. It
B–40 Data Parallel Unit Reference Pages